Patents by Inventor Scott List

Scott List has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8421225
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Publication number: 20120280387
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 8, 2012
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Patent number: 8203208
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 19, 2012
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Publication number: 20110260319
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Application
    Filed: May 9, 2011
    Publication date: October 27, 2011
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Patent number: 7973407
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobrinsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Patent number: 7960226
    Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List, Ruitao Zhang
  • Patent number: 7893481
    Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Richard Scott List, Bruce A. Block, Ruitao Zhang
  • Patent number: 7843036
    Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List
  • Patent number: 7842553
    Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, Alan Myers
  • Patent number: 7723208
    Abstract: Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, James G. Maveety, Alan M. Myers, Quat T. Vu
  • Patent number: 7696015
    Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, James G. Maveety, Alan M. Myers, Quat T. Vu
  • Patent number: 7667319
    Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: February 23, 2010
    Assignee: Intel Corporation
    Inventors: R. Scott List, Alan Myers, Quat T. Vu
  • Patent number: 7615462
    Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, Tom Letson
  • Patent number: 7576432
    Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, James G. Maveety, Alan M. Myers, Quat T. Vu, Ravi Prasher, Ravi Mahajan, Gilroy Vandentop
  • Patent number: 7569426
    Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, R. Scott List, Gilroy J. Vandentop
  • Publication number: 20090174070
    Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 9, 2009
    Inventors: Shriram Ramanathan, Patrick Morrow, Scott List, Michael Y. Chan, Mauro J. Kobnnsky, Sarah E. Kim, Kevin P. O'Brien, Michael C. Harmes, Thomas Marieb
  • Patent number: 7537954
    Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Sarah E. Kim, R. Scott List, Gregory M. Chrysler
  • Publication number: 20080296731
    Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 4, 2008
    Inventors: Bruce A. Block, Richard Scott List
  • Patent number: 7416954
    Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List
  • Patent number: 7355277
    Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 8, 2008
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, R. Scott List, Gilroy J. Vandentop