Patents by Inventor Scott Luning
Scott Luning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262905Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.Type: GrantFiled: September 28, 2015Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning
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Patent number: 10068806Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: GrantFiled: February 26, 2018Date of Patent: September 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Publication number: 20180182674Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: ApplicationFiled: February 26, 2018Publication date: June 28, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Publication number: 20180108571Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Patent number: 9947590Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: GrantFiled: October 14, 2016Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Patent number: 9666488Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.Type: GrantFiled: April 11, 2016Date of Patent: May 30, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Tuhin Guha Neogi, David Pritchard, Scott Luning, Guillaume Bouche, David Doman
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Patent number: 9633911Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.Type: GrantFiled: March 25, 2015Date of Patent: April 25, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning
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Publication number: 20160020154Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.Type: ApplicationFiled: September 28, 2015Publication date: January 21, 2016Inventors: KANGGUO CHENG, BRUCE B. DORIS, ALI KHAKIFIROOZ, QING LIU, NICOLAS LOUBET, SCOTT LUNING
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Patent number: 9219078Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.Type: GrantFiled: April 18, 2013Date of Patent: December 22, 2015Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICOROELECTRONICS, INC., GLOBALFOUNDRIES, INC.Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning
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Publication number: 20150200205Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.Type: ApplicationFiled: March 25, 2015Publication date: July 16, 2015Inventors: KANGGUO CHENG, BRUCE B. DORIS, ALI KHAKIFIROOZ, QING LIU, NICOLAS LOUBET, SCOTT LUNING
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Patent number: 8912603Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.Type: GrantFiled: July 11, 2011Date of Patent: December 16, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Scott Luning, Frank Scott Johnson
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Publication number: 20140312423Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.Type: ApplicationFiled: April 18, 2013Publication date: October 23, 2014Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES Inc., STMicroelectronics, Inc.Inventors: KANGGUO CHENG, BRUCE B. DORIS, ALI KHAKIFIROOZ, QING LIU, NICOLAS LOUBET, SCOTT LUNING
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Patent number: 8404592Abstract: Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width.Type: GrantFiled: July 27, 2009Date of Patent: March 26, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Scott Luning, Frank S. Johnson
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Publication number: 20120171820Abstract: A method is provided for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate that includes a layer of monocrystalline silicon germanium material characterized by a first lattice constant. A strained silicon layer is formed over the layer of monocrystalline silicon germanium material. A layer of gate electrode material is patterned to form a gate electrode overlying a channel region. The strained silicon layer is disposed between the gate electrode and the channel region. First recess and second recesses are etched into the layer of monocrystalline silicon germanium material. A layer of monocrystalline semiconductor material is then epitaxially grown to fill the first and second recesses such that it is embedded at the opposing sides of the channel region. The layer of monocrystalline semiconductor material comprises silicon and germanium, and is characterized by a second lattice constant less than the first lattice constant.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Andrew Michael WAITE, Scott LUNING
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Patent number: 8193592Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.Type: GrantFiled: October 14, 2010Date of Patent: June 5, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
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Patent number: 8148214Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.Type: GrantFiled: January 28, 2009Date of Patent: April 3, 2012Assignee: GlobalFoundries Inc.Inventors: Andrew M. Waite, Scott Luning
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Patent number: 8120120Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 ? to 28 about 800 ?, and the first and second layers at a thickness of about 30 ? to about 70 ?.Type: GrantFiled: September 17, 2009Date of Patent: February 21, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank (Bin) Yang, Johan W. Weijtmans, Scott Luning
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Publication number: 20110266622Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: GLOBALFOUNDRIES Inc.Inventors: Scott Luning, Frank Scott Johnson
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Patent number: 8039349Abstract: Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.Type: GrantFiled: July 30, 2009Date of Patent: October 18, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Michael J. Hargrove, Frank Scott Johnson, Scott Luning
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Patent number: 8030144Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.Type: GrantFiled: October 9, 2009Date of Patent: October 4, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Scott Luning, Frank Scott Johnson