Abstract: A memory system, sensor circuit, and method of operating a memory system are provided. The disclosed memory system includes a first transducer configured to output a first electrical signal indicative of a first operating parameter of the memory system. The memory system is further disclosed to include a second transducer configured to output a second electrical signal indicative of a second operating parameter of the memory system where the second transducer shares a node with the first transducer. The memory system is further disclosed to include a sense amplifier that receives the first electrical signal and the second electrical signal and provide an output responsive to both the first electrical signal and the second electrical signal to a preamplifier Integrated Circuit (IC).

Abstract: A storage system includes a magnetic write head, a magnetic storage medium, a channel circuit comprising a write data output, wherein the channel circuit is operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data from the channel circuit, wherein the preamplifier comprises a number of register pages configured to store pattern dependent write current characteristics for a variety of magnet lengths, and wherein the preamplifier is operable to retrieve the write current characteristics based on magnet lengths and to record data bits on the magnetic storage medium using the write current characteristics.

Abstract: A storage system includes a magnetic write head, a magnetic storage medium, a channel circuit comprising a write data output, wherein the channel circuit is operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data from the channel circuit, wherein the preamplifier comprises a number of register pages configured to store pattern dependent write current characteristics for a variety of magnet lengths, and wherein the preamplifier is operable to retrieve the write current characteristics based on magnet lengths and to record data bits on the magnetic storage medium using the write current characteristics.

Abstract: An apparatus for two-dimensional magnetic recording includes a storage medium, an array of magnetoresistive read heads disposed adjacent the storage medium and spaced to read a data track, a number of leads connected to the array of magnetoresistive read heads, and number of bias circuits connected to the array of read heads by the leads. The bias circuits can be configured to independently bias each of the array of read heads with the array of read heads connected in series or in parallel.

Abstract: An apparatus for two-dimensional magnetic recording includes an array reader with a number of magnetoresistive read sensors configured to read data from a storage medium. The magnetoresistive read sensors have a number of connection terminals, with at least one of the connection terminals being shared by more than one of the magnetoresistive read sensors. The apparatus also includes a number of low-noise amplifiers connected to the connection terminals, each configured to amplify a differential signal from a different one of the magnetoresistive read sensors. The apparatus also includes a number of impedance balancing networks connected to a subset of the connection terminals.

Abstract: An apparatus for correcting crosstalk in an array reader magnetic recording system includes an array reader comprising a number of read heads operable to read data from a magnetic storage medium, a preamplifier configured to amplify the signals from the read heads, and a crosstalk correction circuit configured to reduce crosstalk between signals from the read heads.

Abstract: An apparatus for two-dimensional magnetic recording includes a storage medium, an array of magnetoresistive read heads disposed adjacent the storage medium and spaced to read a data track, wherein the array of magnetoresistive read heads share a common terminal, a number of leads connected to the array of magnetoresistive read heads, with one lead for each of the magnetoresistive read heads, plus a common lead connected to the common terminal, wherein each of the plurality of leads other than the at least one common lead are referenced to the at least one common lead, and a preamplifier connected to the array of magnetoresistive read heads by the plurality of leads and operable to perform pseudo-differential sensing or single-ended sensing of signals from the array of magnetoresistive read heads.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for synchronizing operations in a data storage system.

Abstract: A fly height control circuit includes an input node to receive a digital control signal, an output node to output a control current to a resistive heater element to adjust a spacing between a read/write head and a surface of a storage medium, and control circuitry to process the digital control signal and generate the output control current based on the digital control signal. The control circuitry generates a first reference current based at least in part on the control current output from the output node. The control circuitry controls a slew rate of the first reference current to generate a slew rate controlled reference current. The control circuitry generates a second reference current based on a feedback voltage at the output node. The control circuitry compares the slew rate controlled reference current with the second reference current to adjust the control current output from the output node.

Abstract: A fly height control circuit includes an input node to receive a digital control signal, an output node to output a control current to a resistive heater element to adjust a spacing between a read/write head and a surface of a storage medium, and control circuitry to process the digital control signal and generate the output control current based on the digital control signal. The control circuitry generates a first reference current based at least in part on the control current output from the output node. The control circuitry controls a slew rate of the first reference current to generate a slew rate controlled reference current. The control circuitry generates a second reference current based on a feedback voltage at the output node. The control circuitry compares the slew rate controlled reference current with the second reference current to adjust the control current output from the output node.

Abstract: A recording system employing a magneto-resistive (MR) element senses a resistance value of the MR element and generates one or more MR resistance (MRR) signal values based on the sensed MR element resistance value. The MRR signal values might be, for example, current or voltage values proportional or inversely proportional to the MR element resistance value. The MRR signal values might be employed to control one or more of: i) a unity gain bandwidth of a bias loop for the MR element, ii) an MR read head preamplifier low corner frequency, and iii) a slew rate across the MR element.

Abstract: An apparatus and method for determining a resistance of a magneto-resistive head. A current drawn by the head, in response to a fixed bias voltage across the head, is converted to a zero temperature coefficient current such that when supplied to a resistor connected to an input terminal of a comparator the effects of variations in the resistance value are avoided. An output signal of the comparator indicates the resistance of the magneto-resistive head.

Abstract: A method and apparatus for detecting signal peaks caused by a thermal asperity event in a magnetic recording media to reduce data reading errors introduced by the thermal asperity event. A common mode voltage is determined for differential signals representing data bits read from the magnetic recording media and a threshold voltage produced responsive to the common mode voltage. A comparator determines if either of the differential signals exceeds the threshold voltage, thereby indicating the occurrence of a thermal asperity event.

Abstract: A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.

Abstract: A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.

Abstract: A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.

Abstract: A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.

Abstract: A write driver circuit selectively provides write current through a write head in first and second opposite directions. First and second active devices are driven with first and second pre-drive signals. Third and fourth active devices are driven with third and fourth pre-drive signals. First and second pull-up resistances are provided respectively between the first and second active devices and a fixed voltage, and third and fourth pull-up resistances are provided respectively between the third and fourth active devices and the fixed voltage. A first capacitor is connected between the first active device and an intermediate point of the third pull-up resistance, and a second capacitor is connected between the second active device and an intermediate point of the fourth pull-up resistance.