Patents by Inventor Scott N. Gatzemeier
Scott N. Gatzemeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8687435Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.Type: GrantFiled: March 19, 2013Date of Patent: April 1, 2014Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Wallace E. Fister, Adam D. Johnson, Benjamin S. Louie
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Publication number: 20130229878Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.Type: ApplicationFiled: March 19, 2013Publication date: September 5, 2013Applicant: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Wallace E. Fister, Adam D. Johnson, Benjamin S. Louie
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Patent number: 8094508Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.Type: GrantFiled: July 27, 2009Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Patent number: 8024629Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.Type: GrantFiled: April 26, 2010Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Scott N. Gatzemeier, Adam Johnson, Frankie F. Roohparvar
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Publication number: 20100205490Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.Type: ApplicationFiled: April 26, 2010Publication date: August 12, 2010Inventors: Benjamin Louie, Scott N. Gatzemeier, Adam Johnson, Frankie F. Roohparvar
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Patent number: 7707467Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.Type: GrantFiled: February 23, 2007Date of Patent: April 27, 2010Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Scott N. Gatzemeier, Adam Johnson, Frankie F. Roohparvar
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Publication number: 20090290441Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.Type: ApplicationFiled: July 27, 2009Publication date: November 26, 2009Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Patent number: 7620768Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.Type: GrantFiled: July 10, 2006Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Mitch Liu
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Patent number: 7567472Abstract: A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.Type: GrantFiled: April 12, 2006Date of Patent: July 28, 2009Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Patent number: 7512507Abstract: Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.Type: GrantFiled: March 23, 2006Date of Patent: March 31, 2009Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Joemar D. Sinipete, Robert J. Ringhofer, Nevil Gajera, Mark A. Hawes
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Publication number: 20080209284Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.Type: ApplicationFiled: February 23, 2007Publication date: August 28, 2008Inventors: Benjamin Louie, Scott N. Gatzemeier, Adam Johnson, Frankie F. Roohparvar
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Patent number: 7411848Abstract: A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.Type: GrantFiled: August 23, 2007Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, June Lee
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Patent number: 7292487Abstract: A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.Type: GrantFiled: May 10, 2006Date of Patent: November 6, 2007Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, June Lee
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Patent number: 7168018Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.Type: GrantFiled: May 25, 2004Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Chris Cooper, Siang Tian Giam, Jerry D. McBride, Scott N. Gatzemeier, Scott L. Ayres, David R. Brown
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Patent number: 7116584Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.Type: GrantFiled: August 7, 2003Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Mitch Liu
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Patent number: 6986084Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.Type: GrantFiled: June 29, 2004Date of Patent: January 10, 2006Assignee: Micron Technology, Inc.Inventors: Chris Cooper, Siang Tian Giam, Jerry D. McBride, Scott N. Gatzemeier, Scott L. Ayres, David R. Brown
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Patent number: 6854079Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.Type: GrantFiled: August 31, 2000Date of Patent: February 8, 2005Assignee: Micron Technology, Inc.Inventors: Chris Cooper, Siang Tian Giam, Jerry D. McBride, Scott N. Gatzemeier, Scott L. Ayres, David R. Brown
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Patent number: 6839292Abstract: A method and apparatus for programming programmable elements of a plurality of memory devices in parallel. Each of the memory devices include an address latch for latching an address corresponding to a programmable element to be programmed and logic circuitry for receiving address load commands. The logic circuitry provides control signals to the address latch in response to receiving the load commands to cause the address latch to latch an corresponding to a programmable element to be programmed. By using the address latch and logic circuitry, the programming of a programmable element of a first memory device and the programming the second programmable element of a second memory device can occur in parallel.Type: GrantFiled: December 14, 2001Date of Patent: January 4, 2005Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Wallace E. Fister
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Publication number: 20040255211Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.Type: ApplicationFiled: May 25, 2004Publication date: December 16, 2004Inventors: Chris Cooper, Siang Tian Giam, Jerry D. McBride, Scott N. Gatzemeier, Scott L. Ayres, David R. Brown
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Publication number: 20040233738Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.Type: ApplicationFiled: June 29, 2004Publication date: November 25, 2004Inventors: Chris Cooper, Siang Tian Giam, Jerry D. McBride, Scott N. Gatzemeier, Scott L. Ayres, David R. Brown