Abstract: A static random access memory (14) has a normal mode of operation and a low voltage mode of operation. A memory array (15) includes memory cells (16) coupled to a first power supply node (VDD) for receiving a power supply voltage. A plurality of word line drivers is coupled to word lines of the memory array (15) and to a second power supply node (37). A word line driver voltage reduction circuit (36) has an input coupled to the first power supply node (VDD) and an output coupled to the second power supply node (37) for reducing a voltage on the output in relation to a voltage on the input in response to a low power supply voltage signal, and thus improving a static noise margin of the memory cells (16).

Abstract: A dynamic random access memory has a bit of data selected by a multiplexed address. The row address latches twice as much data as can be selected by the column address which follows the row address. After the column address has been utilized, there is still a one of two selection between two bits of data required. One of the row addresses provides the final selection between the two bits of data. An array toggle signal available from an extra pin is used to switch the state of the internal signal which corresponds to the one row address signal which makes the final one of two selection. The array toggle signal thus makes it possible to access any of the latched data in a high speed mode in which only the column address is changed to select among the bits of data which are already latched.

Abstract: A row decoder includes a logic decoder, a word line driver circuit, and first and second coupling circuits. The logic decoder provides a logic high in an inactive cycle and when selected in an active cycle, and a logic low when deselected in the active cycle. Each of a plurality of word line driver circuits receive a decoded address signal which corresponds to that particular driver circuit, each have an output coupled to a corresponding word line, and each have an input which, when at a logic high, causes that word line driver to couple its corresponding decoded address signal to its corresponding word line. The first coupling circuit couples the output of the logic decoder to the input of only the driver circuit which corresponds to an active decoded address signal during the active cycle, and for coupling the output of the logic decoder to all of the driver circuits in the inactive cycle.

Abstract: A logic decoder provides a true output signal at a first logic state when selected during an active cycle and during an inactive cycle, and at a second logic state when deselected. The logic decoder also provides a complementary output signal. A word line driver circuit couples decoded address signals to respective word lines when the output signal is in the first logic state. A coupling circuit couples one of first and second word lines to ground during the active cycle. A coupling transistor couples the first and second word lines together in response to receiving the complementary output signal at the first logic state.