Patents by Inventor Scott S. Nance
Scott S. Nance has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8293547Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.Type: GrantFiled: March 2, 2011Date of Patent: October 23, 2012Assignee: Xilinx, Inc.Inventors: James Karp, Steven P. Young, Bernard J. New, Scott S. Nance, Patrick J. Crotty
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Publication number: 20110147949Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.Type: ApplicationFiled: March 2, 2011Publication date: June 23, 2011Applicant: XILINX, INC.Inventors: James Karp, Steven P. Young, Bernard J. New, Scott S. Nance, Patrick J. Crotty
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Patent number: 7919845Abstract: Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.Type: GrantFiled: December 20, 2007Date of Patent: April 5, 2011Assignee: Xilinx, Inc.Inventors: James Karp, Steven P. Young, Bernard J. New, Scott S. Nance, Patrick J. Crotty
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Publication number: 20090160482Abstract: Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: Xilinx, Inc.Inventors: James Karp, Steven P. Young, Bernard J. New, Scott S. Nance, Patrick J. Crotty
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Patent number: 6028450Abstract: A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.Type: GrantFiled: March 17, 1998Date of Patent: February 22, 2000Assignee: Xilinx, Inc.Inventor: Scott S. Nance
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Patent number: 5933025Abstract: A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin.Type: GrantFiled: January 15, 1997Date of Patent: August 3, 1999Assignee: Xilinx, Inc.Inventors: Scott S. Nance, Mohammad R. Tamjidi, Richard C. Li, Jennifer Wong, Hassan K. Bazargan
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Patent number: 5877979Abstract: A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell.Type: GrantFiled: June 26, 1997Date of Patent: March 2, 1999Assignee: Xilinx, Inc.Inventors: Richard C. Li, Hy V. Nguyen, Scott S. Nance
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Patent number: 5715197Abstract: A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array to implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word.Type: GrantFiled: July 29, 1996Date of Patent: February 3, 1998Assignee: Xilinx, Inc.Inventors: Scott S. Nance, Douglas P. Sheppard, Nicholas J. Sawyer
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Patent number: RE40423Abstract: A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array in implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word.Type: GrantFiled: May 15, 2001Date of Patent: July 8, 2008Assignee: Xilinx, Inc.Inventors: Scott S. Nance, Douglas P. Sheppard, Nicholas J. Sawyer