Abstract: A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.

Abstract: A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material.

Abstract: A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size.

Abstract: A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing.

Abstract: A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Abstract: A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing.

Abstract: A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

Abstract: A first conductive structure forms a gate electrode of a first transistor of a first transistor type. A second conductive structure forms gate electrodes of both a second transistor of the first transistor type and a first transistor of a second transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms gate electrodes of both a third transistor of the first transistor type and a third transistor of the second transistor type. Gate electrodes of the first and second transistors of the first transistor type are separated by a fixed pitch, as are the gate electrodes of the second and third transistors of the second transistor type. The gate electrodes of the first transistor of the first transistor type and the second transistor of the second transistor type are separated by at least the fixed pitch.

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Abstract: A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size.

Abstract: A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Abstract: A semiconductor device includes a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.