Patents by Inventor Scott Thomas Sheppard
Scott Thomas Sheppard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11587842Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: October 29, 2020Date of Patent: February 21, 2023Assignee: Wolfspeed, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Publication number: 20210043530Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: October 29, 2020Publication date: February 11, 2021Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10886189Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: May 1, 2019Date of Patent: January 5, 2021Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10840162Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: May 1, 2019Date of Patent: November 17, 2020Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Publication number: 20190259682Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 10367074Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: September 26, 2016Date of Patent: July 30, 2019Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 10332817Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: December 1, 2017Date of Patent: June 25, 2019Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Publication number: 20190172769Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
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Patent number: 9934983Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.Type: GrantFiled: February 3, 2014Date of Patent: April 3, 2018Assignee: Cree, Inc.Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
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Publication number: 20170012106Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 9490169Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: November 2, 2010Date of Patent: November 8, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Publication number: 20150221574Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.Type: ApplicationFiled: February 3, 2014Publication date: August 6, 2015Applicant: Cree, Inc.Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
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Patent number: 8202796Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.Type: GrantFiled: February 7, 2011Date of Patent: June 19, 2012Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Publication number: 20110165771Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.Type: ApplicationFiled: February 7, 2011Publication date: July 7, 2011Applicant: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Publication number: 20110108855Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: ApplicationFiled: November 2, 2010Publication date: May 12, 2011Applicant: CREE, INC.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 7892974Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts.Type: GrantFiled: October 20, 2006Date of Patent: February 22, 2011Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 7858460Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.Type: GrantFiled: March 16, 2009Date of Patent: December 28, 2010Assignee: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III
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Publication number: 20090215280Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.Type: ApplicationFiled: March 16, 2009Publication date: August 27, 2009Applicant: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III
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Patent number: 7525122Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.Type: GrantFiled: June 29, 2005Date of Patent: April 28, 2009Assignee: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III
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Publication number: 20090104738Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts.Type: ApplicationFiled: October 20, 2006Publication date: April 23, 2009Applicant: CREE, INC.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner