Patents by Inventor Scott W. Gould
Scott W. Gould has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7961932Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.Type: GrantFiled: October 1, 2007Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Robert J. Allen, John M. Cohn, Scott W. Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez, Ivan L. Wemple, Paul S. Zuchowski
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Patent number: 7496877Abstract: An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.Type: GrantFiled: August 11, 2005Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Andrew D. Huber, Ciaran J. Brennan, Paul E. Dunn, Scott W. Gould, Lin Lin, Erich C. Schanzenbach
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Patent number: 7289659Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.Type: GrantFiled: June 20, 2003Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Robert J. Allen, John M. Cohn, Scott W. Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez, Ivan L. Wemple, Paul S. Zuchowski
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Patent number: 7234124Abstract: A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N?1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.Type: GrantFiled: November 3, 2004Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Bing Chen, Scott W. Gould, Mark Kwang-Jen Hsu, Patrick M. Ryan, Erich C. Schanzenbach
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Patent number: 7131074Abstract: An integrated circuit. The integrated circuit includes a parent terrain; and a hierarchical order of nested voltage islands within the parent terrain, each higher-order voltage island nested within a lower-order voltage island, each nested voltage island having the same hierarchical structure.Type: GrantFiled: July 8, 2003Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Thomas R Bednar, Scott W Gould, David E Lackey, Douglas W Stout, Paul S Zuchowski
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Patent number: 7096436Abstract: Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.Type: GrantFiled: September 21, 2004Date of Patent: August 22, 2006Assignee: International Business Machines CorporationInventors: Thomas R. Bednar, Paul E. Dunn, Scott W. Gould, Jeannie H. Panner, Paul S. Zuchowski
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Patent number: 6883155Abstract: Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.Type: GrantFiled: March 31, 2003Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Thomas R. Bednar, Paul E. Dunn, Scott W. Gould, Jeannie H. Panner, Paul S. Zuchowski
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Patent number: 6883152Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.Type: GrantFiled: June 15, 2004Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Thomas R. Bednar, Scott W. Gould, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski
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Patent number: 6861753Abstract: A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N?1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.Type: GrantFiled: October 9, 2003Date of Patent: March 1, 2005Assignee: International Business Machines CorporationInventors: Bing Chen, Scott W. Gould, Mark Kwang-Jen Hsu, Patrick M. Ryan, Erich C. Schanzenbach
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Publication number: 20040258294Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.Type: ApplicationFiled: June 20, 2003Publication date: December 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Allen, John M. Cohn, Scott W. Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez, Ivan L. Wemple, Paul S. Zuchowski
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Publication number: 20040243958Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.Type: ApplicationFiled: June 15, 2004Publication date: December 2, 2004Inventors: Thomas R. Bednar, Scott W. Gould, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski
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Patent number: 6825711Abstract: An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.Type: GrantFiled: April 30, 2003Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: John M. Cohn, Kenneth J. Goodnow, Scott W. Gould, Douglas W. Stout, Sebastian T. Ventrone
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Patent number: 6820240Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.Type: GrantFiled: September 25, 2002Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Thomas R. Bednar, Scott W. Gould, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski
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Publication number: 20040217805Abstract: An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given execution.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Applicant: International Business Machines CorporationInventors: John M. Cohn, Kenneth J. Goodnow, Scott W. Gould, Douglas W. Stout, Sebastian T. Ventrone
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Patent number: 6802033Abstract: A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.Type: GrantFiled: April 6, 1999Date of Patent: October 5, 2004Assignee: International Business Machines CorporationInventors: Claude L. Bertin, Alvar A. Dean, Kenneth J. Goodnow, Scott W. Gould, Patrick E. Perry, Wilbur D. Pricer, William R. Tonti
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Patent number: 6779163Abstract: A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.Type: GrantFiled: September 25, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Thomas R. Bednar, Scott W. Gould, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski
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Publication number: 20040060024Abstract: A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: Thomas R. Bednar, Scott W. Gould, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski
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Publication number: 20040060023Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: Thomas R. Bednar, Scott W. Gould, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski
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Publication number: 20030204829Abstract: Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.Type: ApplicationFiled: March 31, 2003Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Thomas R. Bednar, Paul E. Dunn, Scott W. Gould, Jeannie H. Panner, Paul S. Zuchowski
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Patent number: 6598206Abstract: A method and system for modifying power rails of an integrated circuit having improved wireability. This is accomplished by initially generating a power railing design of the integrated circuit into a three-dimensional rail based model. Next, analysis of the design is performed as to placement of the power rails in relation to neighboring elements that affects a predefined wireability. Finally, modification of a segment of each power rail that affects wireability is performed so that required power supply to the neighboring elements (e.g., pins, rails etc.) remains unaffected.Type: GrantFiled: May 10, 2001Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: Laura R. Darden, Scott W. Gould, Patrick M. Ryan, Steven J. Urish