Patents by Inventor Scott William Nolan

Scott William Nolan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic pipeline for graphics processing
    Patent number: 9697580
    Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: July 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Liang Li, Andrew Evan Gruber, Guofang Jiao, Zhenyu Qi, Gregory Steve Pitarys, Scott William Nolan
  • DYNAMIC PIPELINE FOR GRAPHICS PROCESSING
    Publication number: 20160132987
    Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 12, 2016
    Inventors: Liang Li, Andrew Evan Gruber, Guofang Jiao, Zhenyu Qi, Gregory Steve Pitarys, Scott William Nolan
  • Texture decompression for graphics processors
    Patent number: 9159114
    Abstract: Various apparatuses and methods are disclosed for processing texture data compressed with a first compression algorithm and texture data compressed with a second compression algorithm. A processing system may be used to determine whether the compressed texture data is compressed with the first or second compression algorithm, and process the compressed texture data using a decompression algorithm corresponding to the compression algorithm used to compress the texture date.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 13, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Rakesh Kumar Dewangan, Ajay Nawandhar, Scott William Nolan, Elina Kamenetskaya
  • TEXTURE DECOMPRESSION FOR GRAPHICS PROCESSORS
    Publication number: 20150131919
    Abstract: Various apparatuses and methods are disclosed for processing texture data compressed with a first compression algorithm and texture data compressed with a second compression algorithm. A processing system may be used to determine whether the compressed texture data is compressed with the first or second compression algorithm, and process the compressed texture data using a decompression algorithm corresponding to the compression algorithm used to compress the texture date.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: Qualcomm Incorporated
    Inventors: Rakesh Kumar DEWANGAN, Ajay NAWANDHAR, Scott William NOLAN, Elina KAMENETSKAYA
  • System and process for flexible queuing of data packets in network switching
    Patent number: 6714553
    Abstract: A process and system for flexibly switching connections of data packet flows between nodes of data processing system networks by dividing data packets into cells and logically linking these cells on multiple queues of linked pointer lists.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: March 30, 2004
    Assignee: Top Layer Networks, Inc.
    Inventors: Nigel T. Poole, Joseph H. Brown, IV, Scott William Nolan, Barry A. Spinney, Richard L. Szmauz