Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

Abstract: A data driver includes output channels configured to output data signals, output controllers selectively outputting data signals having a first arrangement or data signals having a second arrangement to output channel groups each of which includes N output channels in response to arrangement control signals, where N is a positive integer greater than or equal to 2, and a control signal generator outputting the arrangement control signals to the output controllers to control the output controllers.

Abstract: A display device including: a display region including a first pixel region, a second pixel region, and a third pixel region; a dummy region including a first dummy region disposed between the second pixel region and the third pixel region; first, second, and third pixels respectively arranged in the first pixel region, the second pixel region, and the third pixel region in a matrix of vertical lines and horizontal lines; a data converter configured to receive first image data including effective data corresponding to the display region and dummy data corresponding to the dummy region and generate second image data by converting a gray scale value of dummy data corresponding to at least one region of the first dummy region in the first image data into a predetermined first gray scale value, the first gray scale value being between a lowest gray scale value and a highest gray scale value.

Abstract: A display driving circuit includes a clock signal generator which generates a clock signal at a frequency in response to a frequency control signal, a frequency variation determiner which adaptively changes a frequency variation of the clock signal, based on a magnitude of a deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal supplied from the outside, and a frequency controller which generates the frequency control signal which updates the frequency of the clock signal, based on the frequency variation, and provides the frequency control signal to the clock signal generator.

Abstract: A includes a receiver and a controller. The receiver receives data through a first channel. The controller receives a first synchronization signal including a periodic signal through a second channel different from the first channel and outputs a data signal based on the data and the first synchronization signal.

Abstract: Disclosed is a data driving circuit including a noise filter, first through third voltage generators, and an output circuit. The noise filter receives a driving voltage and removes noise from the driving voltage to output a filtered driving voltage. The first voltage generator outputs a first voltage, a second voltage, and a third voltage. The second voltage generator generates a first reference voltage based on the filtered driving voltage, the first voltage, and the second voltage. The third voltage generator generates a second reference voltage based on the filtered driving voltage, the second voltage, and the third voltage. The output circuit outputs a data signal of a voltage level corresponding to an image signal based on the first reference voltage and the second reference voltage.

Abstract: Disclosed is a data driving circuit including a noise filter, first through third voltage generators, and an output circuit. The noise filter receives a driving voltage and removes noise from the driving voltage to output a filtered driving voltage. The first voltage generator outputs a first voltage, a second voltage, and a third voltage. The second voltage generator generates a first reference voltage based on the filtered driving voltage, the first voltage, and the second voltage. The third voltage generator generates a second reference voltage based on the filtered driving voltage, the second voltage, and the third voltage. The output circuit outputs a data signal of a voltage level corresponding to an image signal based on the first reference voltage and the second reference voltage.

Abstract: A display driving circuit includes a clock signal generator which generates a clock signal at a frequency in response to a frequency control signal, a frequency variation determiner which adaptively changes a frequency variation of the clock signal, based on a magnitude of a deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal supplied from the outside, and a frequency controller which generates the frequency control signal which updates the frequency of the clock signal, based on the frequency variation, and provides the frequency control signal to the clock signal generator.

Abstract: A display device includes a display unit including a pixel which displays an image based on a first power voltage and a data signal, a gamma voltage generator which generates gamma voltages, and a data driver which generates the signal using the gamma voltages and provides the data signal to the pixel. The gamma voltage generator generates first and second reference voltages, generates first and second corrected reference voltages by correcting the first and second reference voltages using a target voltage and an external power voltage provided from the display unit in correspondence with the first power voltage, and generates the gamma voltages by dividing the first and second corrected reference voltages. The gamma voltage generator sets the target voltage based on at least one selected from the first reference voltage, the second reference voltage, and a ground voltage.

Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

Abstract: A display device includes: a pixel which emits light at a luminance corresponding to a data voltage applied thereto; and a data driver which supplies the data voltage to the pixel. The data driver includes: a first amplifier which outputs a first reference voltage; a first booster circuit including an input terminal connected to a first input terminal of the first amplifier, and an output terminal connected to a second input terminal of the first amplifier; a second amplifier which outputs a second reference voltage; a resistance string which receives the first and second reference voltages, and generate gamma voltages which are intermediate voltages between the first and second reference voltages; a digital-analog converter which outputs a gamma voltage corresponding to a gray scale of the pixel among the gamma voltages; and a source amplifier which outputs the gamma voltage as the data voltage.

Abstract: A display device includes a display unit including a pixel which displays an image based on a first power voltage and a data signal, a gamma voltage generator which generates gamma voltages, and a data driver which generates the signal using the gamma voltages and provides the data signal to the pixel. The gamma voltage generator generates first and second reference voltages, generates first and second corrected reference voltages by correcting the first and second reference voltages using a target voltage and an external power voltage provided from the display unit in correspondence with the first power voltage, and generates the gamma voltages by dividing the first and second corrected reference voltages. The gamma voltage generator sets the target voltage based on at least one selected from the first reference voltage, the second reference voltage, and a ground voltage.

Abstract: A display device includes a display panel including pixels coupled to a first scan line and a data line, a power supply to supply voltages, a scan driver to provide a first scan signal to the first scan line a plurality of times for a first frame period (FFP), a data driver to supply a data signal to the data line, and a timing controller to control driving of components. The FFP includes: a first active period (FAP), in which the data signal is supplied; and a first blank period (FBP), in which the data signal is not supplied. The power supply provides on-bias power having a first voltage level (FVL) in the FAP, and provides on-bias power having a second voltage level (SVL) in the FBP. The FBP following the FAP includes a first dimming period in which the on-bias power gradually changes from the FVL to the SVL.

Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

Abstract: A display device may include a display panel which includes pixels, a data driver which provides data voltages corresponding to output image data to the pixels, and a data converter which generates a compensation grayscale from reference compensation values for compensating at least one selected from a color shift and a luminance shift corresponding to a temperature based on an input temperature, an input grayscale included in input image data, and an input luminance, and converts the input image data into the output image data based on the compensation grayscale.

Abstract: A display device including a display panel including a scan line, a data line, and a pixel connected thereto, a gate driver, and a source driver including a gamma voltage generator to generate gamma voltages having different voltage levels, a digital-to-analog converter to generate the data voltage corresponding to a gray scale value using the gamma voltages, and a source buffer, in which the gamma voltage generator includes a first resistor string to set a voltage range of the gamma voltages, a second resistor string to set tab gamma voltages corresponding to some of the gamma voltages within the voltage range, gamma buffers to output the tab gamma voltages, and a third resistor string including tabs respectively connected to output terminals of the gamma buffers, the third resistor string being configured to divide a voltage between the tabs to generate the gamma voltages.

Abstract: Disclosed is a data driving circuit including a noise filter, first through third voltage generators, and an output circuit. The noise filter receives a driving voltage and removes noise from the driving voltage to output a filtered driving voltage. The first voltage generator outputs a first voltage, a second voltage, and a third voltage. The second voltage generator generates a first reference voltage based on the filtered driving voltage, the first voltage, and the second voltage. The third voltage generator generates a second reference voltage based on the filtered driving voltage, the second voltage, and the third voltage. The output circuit outputs a data signal of a voltage level corresponding to an image signal based on the first reference voltage and the second reference voltage.

Abstract: A display device including: a display region including a first pixel region, a second pixel region, and a third pixel region; a dummy region including a first dummy region disposed between the second pixel region and the third pixel region; first, second, and third pixels respectively arranged in the first pixel region, the second pixel region, and the third pixel region in a matrix of vertical lines and horizontal lines; a data converter configured to receive first image data including effective data corresponding to the display region and dummy data corresponding to the dummy region and generate second image data by converting a gray scale value of dummy data corresponding to at least one region of the first dummy region in the first image data into a predetermined first gray scale value, the first gray scale value being between a lowest gray scale value and a highest gray scale value.

Abstract: A display device includes a display panel including pixels coupled to a first scan line and a data line, a power supply to supply voltages, a scan driver to provide a first scan signal to the first scan line a plurality of times for a first frame period (FFP), a data driver to supply a data signal to the data line, and a timing controller to control driving of components. The FFP includes: a first active period (FAP), in which the data signal is supplied; and a first blank period (FBP), in which the data signal is not supplied. The power supply provides on-bias power having a first voltage level (FVL) in the FAP, and provides on-bias power having a second voltage level (SVL) in the FBP. The FBP following the FAP includes a first dimming period in which the on-bias power gradually changes from the FVL to the SVL.

Abstract: A display driving circuit includes a clock signal generator which generates a clock signal at a frequency in response to a frequency control signal, a frequency variation determiner which adaptively changes a frequency variation of the clock signal, based on a magnitude of a deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal supplied from the outside, and a frequency controller which generates the frequency control signal which updates the frequency of the clock signal, based on the frequency variation, and provides the frequency control signal to the clock signal generator.