Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a defect detector, and a test controller. The defect detector may generate defect information indicating a defect state in which a value of a cell current measured in a sensing operation on selected memory cells among the plurality of memory cells is less than a threshold value. The test controller may count fail bits from a result of a test operation performed on the selected memory cells using a test reference current in response to the defect information, and set a bit line voltage to be used in the sensing operation based on a comparison result between a number of fail bits detected in the test operation and a reference number.

Abstract: A memory device includes: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, and a verify operation of verifying a program state of the selected memory cells; and a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, and increasing by a second step voltage that is lower than the first step voltage in program loops in a second state that occur after the program loops in the first state. The first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.

Abstract: A method of operating a semiconductor device includes: starting a program operation on selected memory cells among a plurality of memory cells in response to a program command; suspending the program operation in response to a program suspend command; and performing a pre-verify operation by using a modified verify voltage in response to a program resume command.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a fail bit detection operation on memory cells selected from among the plurality of memory cells. The control logic may control the peripheral circuit to set target parameters related to a main operation based on a comparison result between a fail bit detection time measured in the fail bit detection operation and a reference time, and perform the main operation on the selected memory cells based on the target parameters.

Abstract: A memory device includes a plurality of memory cells programmed to a first program state through a plurality of program loops, a page buffer configured to perform a verify operation of verifying the first program state in each of the plurality of program loops, and control logic configured to, as the plurality of program loops are sequentially performed, adjust a first evaluation time of a first evaluation operation so as to decrease the difference between a second evaluation time of a second evaluation operation and the first evaluation time.

Abstract: A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

Abstract: A memory device includes memory cells connected to a plurality of word lines. The memory device also includes a read operation performer configured to perform a read operation of applying an equalizing voltage to the plurality of word lines and applying a read voltage to a selected word line. The memory device further includes a fail cell counter configured to count a number of on cells among selected memory cells connected to the selected word line at each of time points. The memory device additionally includes a read operation controller configured to control the read operation performer to determine a length of an evaluation period based on a result of comparing the number of on cells at each of the time points, and configured to sense a voltage of bit lines respectively connected to the selected memory cells after the evaluation period elapses from the time.

Abstract: A memory device includes a precharge time information storage for storing information on a first precharge time for which a bit line control signal is applied and a second precharge time for which a source line control signal is applied, which are determined according to a degree to which a program operation is performed. The memory device also includes a precharge voltage controller for providing the bit line control signal and the source line control signal respectively to page buffers and a source line driver for a longer precharge time selected from the first precharge time and the second precharge time in the program operation.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit configured to perform a verify operation that identifies threshold voltages of the plurality of memory cells by using a first verify voltage and a second verify voltage, and a program operation controller configured to control the peripheral circuit, after the verify operation is terminated and during a period in which a program voltage is applied to the plurality of memory cells, to apply a first control signal to a page buffer that is coupled to a first memory cell having a threshold voltage that is higher than the first verify voltage and lower than the second verify voltage, and apply a second control signal having a lower level voltage than the first control signal to the page buffer.

Abstract: A memory device, and a method of operating the same, includes a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, a weak word line information storage configured to store information about a weak word line among the plurality of word lines, and a program operation controller configured to control the peripheral circuit such that the program operation is performed in a first program mode or a second program mode depending on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on the information about the weak word line.

Abstract: The present disclosure relates to an electronic device. A memory device includes a plurality of memory cells coupled to a plurality of word lines, a voltage generator generating program-related voltages to be applied to the plurality of word lines, an address decoder transferring the program-related voltages to the plurality of word lines, and an operation controller controlling the voltage generator and the address decoder to apply a program voltage to a selected word line among the plurality of word lines, a second pass voltage to adjacent word lines neighboring the selected word line, a first pass voltage to remaining word lines except for the selected word line and the adjacent word lines, and to apply a ground voltage to the selected word line and the first pass voltage to the adjacent word lines during a first period.

Abstract: A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

Abstract: The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a program operation on the plurality of memory cells and may perform program verify operations each including at least one verify loop corresponding to a plurality of program states programmed in the program operation. The control logic may control the peripheral circuit to perform a verify pulse apply operation and an additional verify pulse apply operation when a target verify loop count exceeds a reference count corresponding to the target program state, and may determine a failure of the program verify operation corresponding to the target program state based on results of the verify pulse apply operation and the additional verify pulse apply operation. A verify voltage of the additional verify pulse apply operation is higher than a verify voltage of the verify pulse apply operation.

Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.

Abstract: The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a program operation on the plurality of memory cells and may perform program verify operations each including at least one verify loop corresponding to a plurality of program states programmed in the program operation. The control logic may control the peripheral circuit to perform a verify pulse apply operation and an additional verify pulse apply operation when a target verify loop count exceeds a reference count corresponding to the target program state, and may determine a failure of the program verify operation corresponding to the target program state based on results of the verify pulse apply operation and the additional verify pulse apply operation. A verify voltage of the additional verify pulse apply operation is higher than a verify voltage of the verify pulse apply operation.

Abstract: The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, peripheral circuits for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuits to perform a detrap operation between a program voltage apply operation and a program verify operation during the program operation, and the peripheral circuits apply a positive set voltage to a source line connected to the selected memory block during the detrap operation.

Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.

Abstract: A memory device, in accordance with a method of operation, may include: a plurality of pages coupled to a common word line and configured to be sequentially selected by different select lines; a program operation controller configured to perform a program operation on a first page that is to be programmed first, among the plurality of pages; and a start loop manager configured to generate start loop information about a program loop in which program verification corresponding to each of a plurality of program states to be formed by threshold voltages of memory cells included in the first page starts, during the program operation on the first page. The program operation controller is further configured to perform a program operation on a second page to be programmed subsequent to the first page, among the plurality of pages, based on the start loop information.

Abstract: A memory device, in accordance with a method of operation, may include: a plurality of pages coupled to a common word line and configured to be sequentially selected by different select lines; a program operation controller configured to perform a program operation on a first page that is to be programmed first, among the plurality of pages; and a start loop manager configured to generate start loop information about a program loop in which program verification corresponding to each of a plurality of program states to be formed by threshold voltages of memory cells included in the first page starts, during the program operation on the first page. The program operation controller is further configured to perform a program operation on a second page to be programmed subsequent to the first page, among the plurality of pages, based on the start loop information.

Abstract: A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.