Abstract: In a method of reading data in a nonvolatile memory device including a plurality of memory cells having a plurality of states including a first state and a second state, a first read operation for the first state is performed, and a second read operation for the second state is performed. To perform the first read operation, cell counts for a valley of the first state are obtained by performing a valley cell count operation for the first state, a first read voltage level for the first state is determined based on the cell counts and at least one first reference parameter for the first state, and a first sensing operation for the first state is performed by using the first read voltage level. To perform the second read operation, a second read voltage level for the second state is determined based on the cell counts and at least one second reference parameter for the second state, and a second sensing operation for the second state is performed by using the second read voltage level.

Abstract: A computing method and device with data sharing are provided. The method includes loading, by a loader, input data of an input feature map stored in a memory in loading units according to a loading order, storing, by a buffer controller, the loaded input data in a reuse buffer of an address rotationally allocated according to the loading order, and transmitting, by each of a plurality of senders, to an executer respective input data corresponding to each output data of respective convolution operations among the input data stored in the reuse buffer, wherein portions of the transmitted respective input data overlap other.

Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.

Abstract: The air conditioner according to an embodiment of the present disclosure includes: a base panel having an inlet formed in one side thereof, and an outlet formed in another side thereof; a variable panel disposed under the base panel and changed in shape to open and close the inlet and the outlet; and a driving device disposed on the base panel and changing a shape of the variable panel, thereby allowing the variable panel to cover the entire lower surface of base panel. In addition, the variable panel may open and close the inlet and the outlet. The variable panel includes: a fixed part disposed between the inlet and the outlet, and fixed in position vertically relative to the base panel; a cover part spaced apart from the fixed part and disposed at a lower side of the inlet or the outlet; and a variable part disposed between the fixed part and the cover part, and changing an inclination angle of the cover part.

Abstract: The air conditioner according to an embodiment of the present disclosure includes: a base panel having a first communication hole formed in one side thereof, and a second communication hole formed in another side thereof; a variable panel disposed under the base panel and changed in shape to open and close the first communication hole and the second communication hole; and a driving device disposed on an upper side of the base panel and changing a position of one side of the variable panel in an up-down direction, so that the variable panel is changed in shape.

Abstract: The air conditioner according to an embodiment of the present disclosure includes: a base panel having a first communication hole formed in one side thereof, and a second communication hole formed in another side thereof; a variable panel disposed under the base panel and changed in shape to open and close the first communication hole and the second communication hole; and a driving device disposed on an upper side of the base panel and changing a position of one side of the variable panel in an up-down direction, so that the variable panel is changed in shape, wherein the variable panel includes: a first cover part disposed under the base panel to open and close the first communication hole; a second cover part disposed under the base panel to open and close the second communication hole; and a variable part disposed between the first cover part and the second cover part, and changing an inclination angle of the first cover part and the second cover part.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Abstract: A neural network method and apparatus is provided. A processor-implemented neural network method includes a processor and a memory storing information, including stored predetermined precision parameters of a layer of a n neural network, about the layer, the method includes obtaining information about the layer in the memory indicative of the number of output classes; determining, based on the obtained information, a precision for the layer based on the number of output classes of the layer, wherein the precision is determined proportionally with respect to the obtained number of output classes; and processing new parameters, with a set precision, for the layer based on the stored parameter.

Abstract: An indoor unit for an air conditioner including: a cabinet assembly forming an external appearance of the indoor unit and having a suction port formed in a rear surface of the cabinet; a filter module movably disposed in rear of the cabinet assembly; a filter module mounted to the filter mounting member and filtering foreign substances in air flowing into the suction port; a mobile member connected to the filter mounting member and moving a position of the filter mounting member; a driving device pressing the mobile member to change the position of the filter mounting member; and a controller configured to, in response to receiving a control command to change the position of the filter mounting member, operate the driving device that presses the mobile member.

Abstract: A method of processing data includes identifying a sparsity among information, included in input data, based on valid information or invalid information included in the input data, rearranging the input data based on the sparsity among the information indicating a distribution of the invalid values included in the input data, and generating, by performing an operation on the rearranged input data in the neural network, an output data.

Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.

Abstract: An electronic device including an antenna is provided. The electronic device includes a housing including a front surface plate, a rear surface plate, and a side surface member, a printed circuit board positioned within the housing, a first support structure, a second support structure, a patch antenna including a flexible printed circuit board disposed on one surface of the first support structure that faces the rear surface plate, a first conductive patch, and a second conductive patch disposed to be spaced apart from the first conductive patch, a conductive pattern disposed on one surface of the second support structure, and a wireless communication circuit electrically connected with the patch antenna and the conductive pattern, and the first conductive patch, the second conductive patch and the conductive pattern are fed from the wireless communication circuit.

Abstract: A neural network method and apparatus is provided. A processor-implemented neural network method includes determining, based on a determined number of classes of input data, a precision for a neural network layer outputting an operation result, and processing parameters of the layer according to the determined precision.

Abstract: A method of processing data in a neural network, includes identifying a sparsity of input data, based on valid information included in the input data in which the input data includes valid values and invalid values, generate rearranged input data, based on a form of the sparsity by rearranging, in the input data, location of at least one of the valid values and the invalid values, and generating, by performing a convolution on the rearranged input data in the neural network, an output.

Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.

Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.

Abstract: Provided are a method of performing a convolution operation between a kernel and an input feature map based on reuse of the input feature map, and a neural network apparatus using the method. The neural network apparatus generates output values of an operation between each of weights of a kernel and an input feature map, and generates an output feature map by accumulating the output values at positions in the output feature map that are set based on positions of the weights in the kernel.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

Abstract: A processor-implemented apparatus includes a forward transform module configured to transform input feature maps (IFMs) by performing a forward transform operation in a Winograd convolution (WinConv) domain, multiply and accumulate array (MAA) units configured to multiply the transformed IFMs by transformed kernels and perform a first inverse transform operation based on results of the multiplying, and an inverse transform module configured to generate output feature maps (OFMs) based on a result of the first inverse transform operation.

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.