Abstract: An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

Abstract: An X-ray imaging apparatus includes an imaging device configured to capture a camera image of a target; a controller configured to stitch a plurality of X-ray images of respective divided regions of the target to generate one X-ray image of the target; and a display configured to display a settings window that provides a GUI for receiving a setting of an X-ray irradiation condition for the respective divided regions, and display the camera image in which positions of the respective divided regions are displayed.

Abstract: A drum washing machine in which laundry-separated substances, introduced into a gap of a packing member sealing an inlet of the washing machine during a washing process, are easily eliminated. The drum washing machine includes a main body having an entrance hole for placing laundry therein and a door opening and closing the entrance hole, a tub installed in the main body and having an opening corresponding to the entrance hole, a packing member to seal a space between the opening of the tub and the entrance hole. The packing member including a bending portion in which laundry-separate substances accumulate, and a recess adjacent to the bending portion, wherein the recess is formed in a user contactable position on the packing member for assisting in easy elimination of the laundry-separated substances accumulated in the bending portion.

Abstract: A method of manufacturing a semiconductor device includes sequential steps of forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. The anti-reflective layer, hard mask layer, and etch stop layer are then partially etched according to a pattern to create an anti-reflective layer pattern, hard mask layer pattern, and etch stop layer pattern. The anti-reflective layer can be formed of a porous plasma silicon oxinitride layer to keep irregular reflections to a minimum. The anti-reflective layer pattern is then etched, followed by an etching of the first conductive layer to form a gate electrode under the etch stop layer pattern. A conformal spacer insulating layer is formed on the whole surface of the semiconductor substrate, and an interlayer insulating layer is formed on the spacer insulating layer so as to fill openings between the gate electrodes.

Abstract: A method of manufacturing a semiconductor device includes sequential steps of forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. The anti-reflective layer, hard mask layer, and etch stop layer are then partially etched according to a pattern to create an anti-reflective layer pattern, hard mask layer pattern, and etch stop layer pattern. The anti-reflective layer can be formed of a porous plasma silicon oxinitride layer to keep irregular reflections to a minimum. The anti-reflective layer pattern is then etched, followed by an etching of the first conductive layer to form a gate electrode under the etch stop layer pattern. A conformal spacer insulating layer is formed on the whole surface of the semiconductor substrate, and an interlayer insulating layer is formed on the spacer insulating layer so as to fill openings between the gate electrodes.

Abstract: A method of forming a contact hole for a semiconductor device, and a method of forming a capacitor for a semiconductor device using the same. An interlayer dielectric layer, a contact mask material layer including of a material having a high etching selectivity with respect to the interlayer dielectric layer, an anti-reflection layer, and a photoresist layer, are formed on a semiconductor substrate. A photoresist pattern is formed from the photoresist layer to expose part of the anti-reflection layer. and a flow process is performed on the photoresist pattern to expose even a smaller amount of the anti-reflection layer. The anti-reflection layer and the contact mask material layer are then etched to expose part of the interlayer dielectric layer, and the interlayer dielectric layer is etched to form a contact hole.

Abstract: A method of forming a contact hole for a semiconductor device, and a method of forming a capacitor for a semiconductor device using the same. An interlayer dielectric layer, a contact mask material layer including of a material having a high etching selectivity with respect to the interlayer dielectric layer, an anti-reflection layer, and a photoresist layer, are formed on a semiconductor substrate. A photoresist pattern is formed from the photoresist layer to expose part of the anti-reflection layer, and a flow process is performed on the photoresist pattern to expose even a smaller amount of the anti-reflection layer. The anti-reflection layer and the contact mask material layer are then etched to expose part of the interlayer dielectric layer, and the interlayer dielectric layer is etched to form a contact hole.

Abstract: Provided is a method for fabricating a stacked capacitor with improved vertical and bottom etching profiles without electrical bridge between adjacent lower electrodes. Conductive layer for a lower electrode is deposited over an insulating layer whose top portion is made of a nitride etching barrier layer. During the etching of the conductive layer and subsequent overetching for lower electrode pattern, the nitride etching barrier layer serves an etching stopper and allows easier formation of polymer buildups on sidewalls of the lower electrode, more particularly on a bottom edge thereof. Resulting polymer buildups serve to prevent unacceptable bottom and sidewall etching of the lower electrode.

Abstract: A cylindrical storage capacitor for a memory cell is disclosed. The cylindrical storage capacitor has a first polysilicon layer for a storage electrode in contact with conductive plug, the first polysilicon layer being a cylindrical structure, and having a hemispherical grain silicon (HGS) grown only at inner and top surfaces of the first polycrystalline silicon layer. The HGS widens the effective surface area of the storage electrode, to thereby secure a target capacitance and prevent adjacent storage capacitors from being micro-bridged. Moreover, the cylindrical first polysilicon pattern layer of which the outer peripheral surface have a fine vertical profile can be obtained by applying the nitride film as an etch stopper when forming the opening part in a selected portion of the first insulating layer.

Abstract: A multiple tubular shaped capacitor electrode of a semiconductor capacitor with an increased surface area and a method for fabricating thereof. The multiple tubular shaped capacitor includes at least two tubular shapes whose side portions are overlapped with each other. The multiple tubular shaped capacitor is made by forming an insulating layer over an etch stop layer including a contact plug, partially etching the insulating layer down to the contact plug and etch stop layer to form an opening composed of at least two upright cylindrical openings with side portions that define an overlap, and forming a conductive layer on a bottom and both side walls of the opening to form a storage node composed of at least two upright tubular shapes which are attached together at a vertical side section which defines an overlap portion of both tubular shapes to form a capacitor storage node.

Abstract: A plasma etching apparatus is provided having a sealing member coupling an upper electrode to the plasma etching chamber. A peripheral portion of the inner surface of the upper electrode includes a planar surface across both anodized and non-anodized portions of the surface in the peripheral contact region adjacent to the upper portion of the sidewalls of the chamber assembly. A sealing member is positioned between the planar, peripheral portion of the second electrode and the upper portion of the sidewalls to provide a seal therebetween. The anodized portion of the inner surface of the upper electrode may extend over the area adjacent to the opening in the chamber housing and further extend into the peripheral portion beyond the sealing member to reduce the potential for arcing to occur to the non-anodized section during plasma etching operations.