Abstract: A method of recovering a solvent including: supplying polymerization reactants including one or more monomers and a solvent to a reactor to obtain a polymer solution; supplying a stream including the polymer solution to a separator to separate an upper discharge stream including the solvent, wherein the solvent is in a gaseous phase, and a lower discharge stream including the polymer solution; heating a divergence stream including a part of the lower discharge stream from the separator by a heating device and refluxing the divergence stream to the separator; supplying a residue stream including a remainder of the lower discharge stream from the separator to a steam stripping process unit; and adjusting a vapor mass fraction of the divergence stream which is refluxed to the separator with a pressure adjustment valve after being heated by the heating device.

Abstract: An image sensing device is disclosed. The image sensing device includes a plurality of unit pixels arranged as an array of unit pixels in a first direction and a second direction perpendicular to the first direction, and a device isolation structure wherein each of the unit pixels is disposed in a region isolated from adjacent unit pixels and includes a single photoelectric conversion element, a single floating diffusion region, and at least three transistors. The single photoelectric conversion element, the single floating diffusion region, and the at least three transistors are located in a region isolated by the device isolation structure.

Abstract: An image sensing device is disclosed. The image sensing device includes a plurality of unit pixels arranged as an array of unit pixels in a first direction and a second direction perpendicular to the first direction, and a device isolation structure wherein each of the unit pixels is disposed in a region isolated from adjacent unit pixels and includes a single photoelectric conversion element, a single floating diffusion region, and at least three transistors. The single photoelectric conversion element, the single floating diffusion region, and the at least three transistors are located in a region isolated by the device isolation structure.

Abstract: A high voltage integrated device includes a semiconductor layer having a first conductivity, a source region having a second conductivity and a drift region having the second conductivity which are disposed in the semiconductor layer and spaced apart from each other by a channel region, a drain region having the second conductivity and disposed in the drift region, a gate insulation layer disposed over the channel region, a first field insulation layer and a second field insulation layer which are disposed over the drift region and between the channel region and the drain region, wherein the first field insulation layer and the second field insulation layer are spaced apart from each other, an insulation layer disposed over the drift region and located between the first and second field insulation layers, and a gate electrode disposed over the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer, wherein the first field insulation layer is adjace

Abstract: The present invention provides an address-based social safety network system of a smart grid infrastructure device, the address-based social safety network system comprising: a potable location information terminal for transmitting an emergency signal through a RF modem when an emergency signal generation command is inputted; a digital energy meter which calculates an average value of wireless reception strength of the emergency signal received from the portable location information terminal and then transmits the calculated average value to an upper end; a collection device which collects the emergency signal received from the digital energy meter, and which transmits the collected emergency signal to the upper end; and a positioning server which collects the emergency signal received from the collection device, and which tracks location information of the portable location information terminal by using the wireless receiving sensitivity and an intrinsic identification address of the digital emergency meter.

Abstract: The present invention provides an address-based social safety network system of a smart grid infrastructure device, the address-based social safety network system comprising: a potable location information terminal for transmitting an emergency signal through a RF modem when an emergency signal generation command is inputted; a digital energy meter which calculates an average value of wireless reception strength of the emergency signal received from the portable location information terminal and then transmits the calculated average value to an upper end; a collection device which collects the emergency signal received from the digital energy meter, and which transmits the collected emergency signal to the upper end; and a positioning server which collects the emergency signal received from the collection device, and which tracks location information of the portable location information terminal by using the wireless receiving sensitivity and an intrinsic identification address of the digital emergency meter.

Abstract: A semiconductor device includes a substrate having a supporting substrate, wherein a first epitaxial layer and a second epitaxial are sequentially stacked, an isolation region including a first buried impurity region of a second conductivity type and a second buried impurity region of the second conductivity type wherein the first buried impurity region is formed from the supporting substrate to the first epitaxial layer, and the second buried impurity region is formed from the first epitaxial layer to the second epitaxial layer and is in contact with an edge of the first buried impurity region, a third buried impurity region of a first conductivity type formed from the first epitaxial layer to the second epitaxial layer, located in the second buried impurity region and overlapped with the first buried impurity region, and a transistor formed over the second epitaxial layer and overlapped with the third buried impurity region.

Abstract: A semiconductor device test system is disclosed. The semiconductor device test system extends driver- and comparator-functions acting as important functions of a test header to an external part (e.g., a HIFIX board) of the test header, such that it can double the productivity of a test without upgrading the test header. The semiconductor device test system includes a test header for testing a semiconductor device by a test controller, and a HIFIX board for establishing an electrical connection between the semiconductor device and the test header, and including a Device Under Test (DUT) test unit which processes a read signal generated from the semiconductor device by making one pair with a driver of the test header and transmits the processed read signal to the test header.

Abstract: An apparatus for multiplying a semiconductor test pattern signal, which firstly encodes a plurality of pattern signals to have different pattern types, and multiplies the encoded pattern signals according to an exclusive-OR (XOR) scheme in order to generate a single pattern signal, thereby recognizing a relationship between a pattern signal before the multiplication and the other pattern signal after the multiplication. A pattern-signal segmenting/outputting unit segments a semiconductor test pattern signal into a plurality of pattern signals, and simultaneously outputs the segmented pattern signals.

Abstract: A semiconductor device test system is disclosed. The semiconductor device test system extends driver- and comparator-functions acting as important functions of a test header to an external part (e.g., a HIFIX board) of the test header, such that it can double the productivity of a test without upgrading the test header. The semiconductor device test system includes a test header for testing a semiconductor device by a test controller, and a HIFIX board for establishing an electrical connection between the semiconductor device and the test header, and including a Device Under Test (DUT) test unit which processes a read signal generated from the semiconductor device by making one pair with a driver of the test header and transmits the processed read signal to the test header.

Abstract: An apparatus for multiplying a semiconductor test pattern signal is disclosed. The multiplying apparatus firstly encodes a plurality of pattern signals to have different pattern types, and multiplies the encoded pattern signals according to an exclusive-OR (XOR) scheme in order to generate a single pattern signal, thereby recognizing a relationship between a pattern signal before the multiplication and the other pattern signal after the multiplication. A pattern-signal segmenting/outputting unit segments a semiconductor test pattern signal into a plurality of pattern signals, and simultaneously outputs the segmented pattern signals.

Abstract: A calibration method and a semiconductor testing apparatus, including N drivers, N being a natural number no less than two, at least one transmission path coupled to at least one of the N drivers, at least one calibration board coupled to the at least one transmission path, N comparators, and N delay paths, such that each delay path of the N delay paths has a skew value and is coupled between the calibration board and one of the N comparators.

Abstract: A calibration jig for adjusting timing and an apparatus equipped with such a calibration jig, including calibration block, at least one calibration board attached to the calibration block to form a securing platform for at least one test component, and a plurality of calibration terminals integral to the calibration board to provide improved calibration accuracy and timing.

Abstract: Products containing asiatic acid or asiaticoside, and uses thereof, for the treatment of cancer and other proliferative diseases are provided.

Abstract: A method of inhibiting proteolytic degradation of a thermally-stable intracellular protein is described. The method involves adding 1 or more denaturing agents to a sample which contains the protease and the protein of interest and heating the resulting solution at a temperature and for period of time sufficient to denature the protease. The method optionally includes a step for lysing the cell if the protein of interest is contained in a cell in order to release said protein. Additionally, a method of determining Mx protein induced by interferon in a blood sample is described. The method involves adding to a blood sample a lysing agent, a denaturing agent, and a detergent selected to solubilize Mx protein. The sample containing Mx protein is then heated at a temperature of from about 50.degree. C. to about 60.degree. C. for a period of time of from about 1 minute to about 30 minutes, and the Mx protein in the solution then is determined.

Abstract: A process for detecting cancer in a human patient is provided wherein a blood serum is recovered from the patient and is reacted with a monoclonal antibody comprising anti-haptoglobin variant under conditions to effect an immunoreaction when an immunosuppressive factor having a molecular weight of about 50K Daltons is present in the serum. The presence of immunosuppressive factor at concentration levels substantially exceeding normal concentration levels indicates the existence of immunoincompetence due to widely spread cancer. The effectiveness of cancer therapy is monitored by monitoring the change in levels of the immunosuppressive haptoglobin variant factor in the serum from the patient being treated.

Abstract: A high purity immunosuppression factor (IF) having a molecular weight of about 50,000 or a reduced IF having a molecular weight of about 25,000 derived from the higher molecular weight IF and which is stable in dilute aqueous solutions is obtained from human ascites fluid. An extract of human ascites fluid is subjected to chromatography to recover a component of the ascites fluid rich in the immunosuppression factor and containing proteinaceous material which does not degrade the IF factor. The pure IF is obtained by subjecting the component rich in IF to contact with solid phase anti-human IgG (Fc specific) to recover pure IF having a molecular weight of above 50,000. The reduced IF is obtained by heating the higher molecular weight IF.