Patents by Inventor Se Ra Won

Se Ra Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7939855
    Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: May 10, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Yeop Han, Se-Ra Won
  • Publication number: 20090294770
    Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.
    Type: Application
    Filed: August 10, 2009
    Publication date: December 3, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Yeop HAN, Se-Ra Won
  • Patent number: 7572720
    Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: August 11, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Yeop Han, Se-Ra Won
  • Publication number: 20080272431
    Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 6, 2008
    Inventors: Jong Man KIM, Chang Goo LEE, Jong Sik KIM, Se Ra WON
  • Patent number: 7413969
    Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: August 19, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong Man Kim, Chang Goo Lee, Jong Sik Kim, Se Ra Won
  • Publication number: 20070215875
    Abstract: A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches.
    Type: Application
    Filed: December 28, 2006
    Publication date: September 20, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Yeop Han, Se-Ra Won