Patents by Inventor Se Yeong HUH

Se Yeong HUH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for using an error correction code in a memory system
    Patent number: 11442811
    Abstract: Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Bi Woong Chung, Jung Hwan Lee, Se Yeong Huh, In Jae Koo
  • APPARATUS AND METHOD FOR USING AN ERROR CORRECTION CODE IN A MEMORY SYSTEM
    Publication number: 20220269560
    Abstract: Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.
    Type: Application
    Filed: July 16, 2021
    Publication date: August 25, 2022
    Inventors: Bi Woong CHUNG, Jung Hwan LEE, Se Yeong HUH, In Jae KOO