Patents by Inventor Sean Barstow
Sean Barstow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240132993Abstract: Provided are modified bacteria for use in bioleaching rare earth elements (REEs). The modified bacteria contain at least one engineered genetic change that is correlated with improved bioleaching of the REEs, relative to REE bioleaching by unmodified bacteria of the same species as the modified bacteria. Also provided is a method for extracting REEs by contacting a composition containing REEs with biolixiviant produced by the modified bacteria. Kits that include containers that hold the modified bacteria are also provided.Type: ApplicationFiled: February 18, 2022Publication date: April 25, 2024Inventors: Buz BARSTOW, Alexa SCHMITZ, Brooke PIAN, Sean MEDIN
-
Patent number: 9397292Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.Type: GrantFiled: October 2, 2014Date of Patent: July 19, 2016Assignee: Intermolecular, Inc.Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sunil Shanker
-
Publication number: 20160181380Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Amol Joshi, Sean Barstow, Paul Besser, Ashish Bodke, Guillaume Bouche, Nobumichi Fuchigami, Zhendong Hong, Shaoming Koh, Albert Sanghyup Lee, Salil Mujumdar, Abhijit Pethe, Mark Victor Raymond
-
Patent number: 9297775Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.Type: GrantFiled: May 23, 2014Date of Patent: March 29, 2016Assignee: Intermolecular, Inc.Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
-
Publication number: 20150338362Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: Intermolecular Inc.Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
-
Publication number: 20150179508Abstract: Embodiments described herein provide tantalum-based copper barriers and methods for forming such barriers. A dielectric body is provided. A first layer is formed above the dielectric body. The first layer includes tantalum. A second layer is formed above the first layer. The second layer includes manganese. A third layer is formed above the second layer. The third layer includes copper.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Applicant: INTERMOLECULAR INC.Inventors: Edwin Adhiprakasha, Sean Barstow, Frank Greer, Wenxian Zhu
-
Patent number: 9029232Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.Type: GrantFiled: May 19, 2014Date of Patent: May 12, 2015Assignee: Intermolecular, Inc.Inventors: Sandra G Malhotra, Sean Barstow, Tony P. Chiang, Wayne R French, Pragati Kumar, Prashant B Phatak, Sunil Shanker, Wen Wu
-
Patent number: 9030862Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.Type: GrantFiled: September 17, 2014Date of Patent: May 12, 2015Assignee: Intermolecular, Inc.Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sandra G Malhotra
-
Publication number: 20150056748Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.Type: ApplicationFiled: October 2, 2014Publication date: February 26, 2015Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sunil Shanker
-
Publication number: 20150034896Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.Type: ApplicationFiled: September 17, 2014Publication date: February 5, 2015Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sandra G Malhotra
-
Patent number: 8889547Abstract: Provided are methods and systems for forming discreet multilayered structures. Each structure may be deposited by in situ deposition of multiple layers at one of multiple site isolation regions provided on the same substrate for use in combinatorial processing. Alignment of different layers within each structure is provided by using two or more differently sized openings in-between one or more sputtering targets and substrate. Specifically, deposition of a first layer is performed through the first opening that defines a first deposition area. A shutter having a second smaller opening is then positioned in-between the one or more targets and substrate. Sputtering of a second layer is then performed through this second opening that defines a second deposition area. This second deposition area may be located within the first deposition area based on sizing and alignment of the openings as well as alignment of the substrate.Type: GrantFiled: October 3, 2013Date of Patent: November 18, 2014Assignee: Intermolecular, Inc.Inventors: Sean Barstow, Owen Ho Yin Fong
-
Patent number: 8877550Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.Type: GrantFiled: February 10, 2012Date of Patent: November 4, 2014Assignee: Intermolecular, Inc.Inventors: Pragati Kumar, Sean Barstow, Sunil Shanker, Tony Chiang
-
Patent number: 8873276Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.Type: GrantFiled: October 21, 2013Date of Patent: October 28, 2014Assignee: Intermolecular, Inc.Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sandra G Malhotra
-
Publication number: 20140264281Abstract: Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-? dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.Type: ApplicationFiled: December 20, 2013Publication date: September 18, 2014Applicant: Intermolecular, Inc.Inventors: Sandip Niyogi, Sean Barstow, Chi-I Lang, Ratsamee Limdulpaiboon, Dipankar Pramanik, J. Watanabe
-
Publication number: 20140273525Abstract: Metal-oxide films (e.g., aluminum oxide) with low leakage current suitable for high-k gate dielectrics are deposited by atomic layer deposition (ALD). The purge time after the metal-deposition phase is 5-15 seconds, and the purge time after the oxidation phase is prolonged beyond 60 seconds. Prolonging the post-oxidation purge produced an order-of-magnitude reduction of leakage current in 30 ?-thick Al2O3 films.Type: ApplicationFiled: September 6, 2013Publication date: September 18, 2014Applicant: Intermolecular, Inc.Inventors: Kurt Pang, Sean Barstow, Chi-I Lang, Michael Miller, Sandip Niyogi, Prashant B. Phatak
-
Publication number: 20140273309Abstract: Remote-plasma treatments of surfaces, for example in semiconductor manufacture, can be improved by preferentially exposing the surface to only a selected subset of the plasma species generated by the plasma source. The probability that a selected species reaches the surface, or that an unselected species is quenched or otherwise converted or diverted before reaching the surface, can be manipulated by introducing additional gases with selected properties either at the plasma source or in the process chamber, varying chamber pressure or flow rate to increase or decrease collisions, or changing the dimensions or geometry of the injection ports, conduits and other passages traversed by the species. Some example processes treat surfaces preferentially with relatively low-energy radicals, vary the concentration of radicals at the surface in real time, or clean and passivate in the same unit process.Type: ApplicationFiled: October 10, 2013Publication date: September 18, 2014Applicant: Intermolecular, Inc.Inventors: Sandip Niyogi, Sean Barstow, Jay Dedontney, Chi-I Lang, Ratsamee Limdulpaiboon, Martin Romero, Sunil Shanker, James Tsung, J. Watanabe
-
Publication number: 20140256111Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: Intermolecular Inc.Inventors: Sandra G. Malhotra, Sean Barstow, Tony P. Chiang, Wayne R. French, Pragati Kumar, Prashant B. Phatak, Sunil Shanker, Wen Wu
-
Patent number: 8784572Abstract: A method for cleaning platinum residues from a surface of a substrate is provided. The method initiates with exposing the surface to a first solution containing a mixture of nitric acid and hydrochloric acid. Then, the surface is exposed to a second solution containing hydrochloric acid.Type: GrantFiled: October 19, 2011Date of Patent: July 22, 2014Assignee: Intermolecular, Inc.Inventors: Anh Duong, Sean Barstow, Olov Karlsson, Bei Li, James Mavrinac
-
Patent number: 8765567Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.Type: GrantFiled: October 24, 2013Date of Patent: July 1, 2014Assignee: Intermolecular, Inc.Inventors: Sandra G Malhotra, Sean Barstow, Tony P. Chiang, Pragati Kumar, Prashant B Phatak, Sunil Shanker, Wen Wu
-
Publication number: 20140179095Abstract: Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided. A metallic layer is deposited on the germanium oxide layer. The metallic layer may be nanocrystalline or amorphous. The deposition of the metallic layer causes the germanium oxide layer to be reduced such that a metal oxide layer is formed adjacent to the germanium channel.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: INTERMOLECULAR, INC.Inventors: Sandip Niyogi, Sean Barstow, Chi-I Lang