Abstract: Systems and methods for securely provisioning HTTPS pins to a mobile client are provided herein. In some embodiments, the method may comprise receiving, at a mobile client, a digitally signed mobile client configuration file, wherein the mobile client configuration file comprises one or more URLs and one or more key pins associated with services available from the one or more URLs; retrieving a public key from a public key store; verifying a digital signature of the mobile client configuration file using the public key; and storing the key pins on the mobile client when the digital signature is verified.

Abstract: This invention concerns an automated method of generating a design for an I/O fabric of a target integrated circuit having a core and pins. A process tool executes algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language. It imports integrated circuit design data, and from it captures I/O specification data for a circuit core, library of cells, pin, I/O control, BSR and I/O cell chaining, and die. The tool validates the specification data, and generates the I/O fabric design by configuring and inter-connecting a pin multiplexing and control matrix structures according to constraints for signal control, and timing. The structures includes on both the input and output paths of each pin a functional multiplexer matrix structure, a test multiplexer matrix structure, an override matrix structure, a multiplex select and control matrix structure, and an I/O Cell control logic.

Abstract: This invention concerns an automated method of generating a design for an I/O fabric of a target integrated circuit having a core and pins. A process tool executes algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language. It imports integrated circuit design data, and from it captures I/O specification data for a circuit core, library of cells, pin, I/O control, BSR and I/O cell chaining, and die. The tool validates the specification data, and generates the I/O fabric design by configuring and inter-connecting a pin multiplexing and control matrix structures according to constraints for signal control, and timing. The structures includes on both the input and output paths of each pin a functional multiplexer matrix structure, a test multiplexer matrix structure, an override matrix structure, a multiplex select and control matrix structure, and an I/O Cell control logic.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Abstract: A system on a chip has a plurality of processors coupled to a common memory and a hardware protection block which extracts a source ID and memory address data from a memory transaction to determine whether the transaction is destined for a permitted region of memory allotted to the respective processor.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths