Abstract: A forward error correction decoder and method of decoding a codeword is provided. The decoder comprises a convergence processor for estimating an expectation of codeword convergence. The convergence processor is configured to calculate a first value of a figure of merit; calculate a second value of the figure of merit; combine the second value of the figure of merit and the first value of the figure of merit to produce a progress value; compare the progress value of the decoding to a progress threshold; and increase a maximum number of iterations of the decoder if the progress value is greater than the progress threshold. The maximum number of iterations may be initially set to a low number beneficial for power consumption and raw throughput. Increasing the maximum number of iterations devotes additional resources to a particular codeword and is beneficial for error rate performance.

Abstract: A method for boost floor mitigation during a decoding operation performed by a decoder is disclosed herein. The method includes: monitoring for a floor error condition while performing the decoding operation; if a floor error condition has been detected, then: clearing a feedback delay memory in the decoder; downscaling main memory values in the decoder; applying a gain in low-rank columns; and continuing to perform the decoding operation.

Abstract: Forward error correction (FEC) decoders, such as Low Density Parity Check (LDPC) decoders are described. Described FEC decoders minimize the number of internal bits in a layered processor of an LDPC decoder while maintaining high coding gain operation of the LDPC decoder. Minimizing the number of internal bits in a layered processor is achieved by non-linearly companding the soft information into lower precision format while maintaining the dynamic range of the data bits. Described FEC decoders may generate updated soft information having a precision that is equal to the channel precision.

Abstract: An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.

Abstract: A fast Fourier transform processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel interleaver. The modified butterfly unit is obtained by the removal of complex variable multipliers, which is possible due to the simplification of twiddle factors in the stages that correspond to the modified butterfly unit.

Abstract: An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.