Patents by Inventor Sean Gulley
Sean Gulley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036865Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: June 17, 2023Publication date: February 1, 2024Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 11681530Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: March 7, 2022Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20230101226Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.Type: ApplicationFiled: August 26, 2022Publication date: March 30, 2023Applicant: Tahoe Research, Ltd.Inventors: Wajdi FEGHALI, Vinodh GOPAL, Kirk S. YAP, Sean GULLEY, Raghunandan MAKARAM
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Patent number: 11567772Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: November 29, 2021Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 11494320Abstract: Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.Type: GrantFiled: September 24, 2018Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Simon N Peffers, Kirk S Yap, Sean Gulley, Vinodh Gopal, Wajdi Feghali
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Patent number: 11494222Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.Type: GrantFiled: December 18, 2020Date of Patent: November 8, 2022Assignee: Tahoe Research, Ltd.Inventors: Wajdi Feghali, Vinodh Gopal, Kirk S. Yap, Sean Gulley, Raghunandan Makaram
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Publication number: 20220188114Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20220147356Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: November 29, 2021Publication date: May 12, 2022Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 11188335Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: November 2, 2020Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20210149704Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.Type: ApplicationFiled: December 18, 2020Publication date: May 20, 2021Inventors: Wajdi FEGHALI, Vinodh GOPAL, Kirk S. YAP, Sean GULLEY, Raghunandan MAKARAM
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Publication number: 20210049013Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 10924591Abstract: Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios.Type: GrantFiled: June 21, 2018Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Wajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Simon Peffers
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Patent number: 10871983Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.Type: GrantFiled: September 28, 2018Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Wajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Raghunandan Makaram
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Patent number: 10824428Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: GrantFiled: March 29, 2019Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Publication number: 20200310802Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
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Patent number: 10503510Abstract: A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj?16 XOR Wj?9 XOR (Wj?3<<<15)) XOR(Wj?13<<<7)XOR Wj?6 P1 is a permutation function, P1(X)=X XOR (X<<<15) XOR (X<<<23). Wj?16, Wj?9, Wj?3, Wj?13, and Wj?6 are messages associated with a compression function of an SM3 hash function. XOR is an exclusive OR operation. <<< is a rotate operation. An execution unit coupled with the decode unit that is operable, in response to the instruction, to store a result packed data in a destination storage location. The result packed data to include a Wj message to be input to a round j of the compression function.Type: GrantFiled: December 27, 2013Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Gilbert M. Wolrich, Vinodh Gopal, Kirk S. Yap, Wajdi K. Feghali, Sean Gulley
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Publication number: 20190042496Abstract: Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.Type: ApplicationFiled: September 24, 2018Publication date: February 7, 2019Inventors: Simon N. Peffers, Kirk S. Yap, Sean Gulley, Vinodh Gopal, Wajdi Feghali
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Publication number: 20190042481Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.Type: ApplicationFiled: September 28, 2018Publication date: February 7, 2019Inventors: Wajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Raghunandan Makaram
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Publication number: 20190045031Abstract: Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios.Type: ApplicationFiled: June 21, 2018Publication date: February 7, 2019Inventors: Wajdi Feghali, Vinodh Gopal, Kirk Yap, Sean Gulley, Simon Peffers
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Patent number: 9503256Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.Type: GrantFiled: December 24, 2014Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Kirk Yap, Gilbert Wolrich, Sudhir Satpathy, Sean Gulley, Vinodh Gopal, Sanu Mathew, Wajdi Feghali