Patents by Inventor Sean Xuan Lin
Sean Xuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10580696Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.Type: GrantFiled: August 21, 2018Date of Patent: March 3, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
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Publication number: 20200066585Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
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Patent number: 10573593Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.Type: GrantFiled: May 18, 2018Date of Patent: February 25, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Sean Xuan Lin, Xunyuan Zhang, Shao Beng Law, James Jay McMahon
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Patent number: 10395926Abstract: Methods of self-aligned multiple patterning. A mandrel line is formed over a hardmask layer, and forming a block mask is formed over a first portion of the mandrel line that is linearly arranged between respective second portions of the mandrel line. After forming the first block mask, the second portions of the mandrel line are removed with an etching process to cut the mandrel line and expose respective portions of the hardmask layer. A second portion of the mandrel line is covered by the block mask during the etching process to define a mandrel cut in the mandrel line.Type: GrantFiled: April 17, 2018Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Minghao Tang, Yuping Ren, Sean Xuan Lin, Shao Beng Law, Genevieve Beique, Xun Xiang, Rui Chen
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Patent number: 10283372Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.Type: GrantFiled: September 15, 2017Date of Patent: May 7, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Sean Xuan Lin, Xunyuan Zhang, Mark V. Raymond, Errol Todd Ryan, Nicholas V. LiCausi
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Publication number: 20190088500Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Sean Xuan Lin, Xunyuan Zhang, Mark V. Raymond, Errol Todd Ryan, Nicholas V. LiCausi
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Publication number: 20190019726Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Applicant: GLOBALFOUNDRIES Inc.Inventors: Errol Todd RYAN, Sean Xuan LIN
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Patent number: 10181421Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.Type: GrantFiled: July 12, 2017Date of Patent: January 15, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Errol Todd Ryan, Sean Xuan Lin
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Patent number: 10134580Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.Type: GrantFiled: August 15, 2017Date of Patent: November 20, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Nicholas V. LiCausi, Errol Todd Ryan, Sean Xuan Lin
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Patent number: 10103029Abstract: A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.Type: GrantFiled: May 6, 2016Date of Patent: October 16, 2018Assignee: MacDermid Enthone Inc.Inventors: Thomas B. Richardson, Joseph A. Abys, Wenbo Shao, Chen Wang, Vincent Paneccasio, Cai Wang, Sean Xuan Lin, Theodore Antonellis
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Publication number: 20180269150Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.Type: ApplicationFiled: May 18, 2018Publication date: September 20, 2018Inventors: Sean Xuan LIN, Xunyuan ZHANG, Shao Beng LAW, James Jay McMahon
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Patent number: 10026687Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.Type: GrantFiled: February 20, 2017Date of Patent: July 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sean Xuan Lin, Xunyuan Zhang, Shao Beng Law, James Jay McMahon
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Patent number: 9805972Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; an upper wiring layer with one or more wiring structures, located above the first wiring layer; a blocking material which contacts at least one of the wiring structures of the upper wiring layer; a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.Type: GrantFiled: February 20, 2017Date of Patent: October 31, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xunyuan Zhang, Sean Xuan Lin, James Jay McMahon, Shao Beng Law
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Patent number: 9425103Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.Type: GrantFiled: December 4, 2014Date of Patent: August 23, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Chanro Park, Sean Xuan Lin
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Publication number: 20160163601Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.Type: ApplicationFiled: December 4, 2014Publication date: June 9, 2016Inventors: Ruilong Xie, Chanro Park, Sean Xuan Lin
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Patent number: 9299745Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.Type: GrantFiled: May 8, 2014Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Xunyuan Zhang, Sean Xuan Lin, Kunaljeet Tanwar
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Publication number: 20150325622Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Xunyuan Zhang, Sean Xuan Lin, Kunaljeet Tanwar
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Patent number: 8907483Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).Type: GrantFiled: October 10, 2012Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin
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Patent number: RE47630Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).Type: GrantFiled: October 26, 2016Date of Patent: October 1, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin
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Patent number: RE49820Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).Type: GrantFiled: August 31, 2019Date of Patent: January 30, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Larry Zhao, Ming He, Xunyuan Zhang, Sean Xuan Lin