Abstract: A variable gain analog amplifier is described that uses pulse-density modulation in the form of a sigma-delta modulator (SDM) to produce a gain by modulating the selection of a switch that selects the amount of resistance in a negative feedback loop of the amplifier. The output of the SDM is dithered to increase the gain resolution of the analog amplifier, wherein the increased resolution produces a quiet, inaudible transition between changes in gain setting at an output of the variable gain amplifier and in addition produces a quiet, inaudible mixing and merging of audio signals.

Abstract: A digital active noise cancellation circuit device (330) includes an oversampled, sigma-delta, A/D converter (204), a digital decimation filter (208), a digital intermediate filter (308), a digital interpolation filter (232), and a sigma-delta, D/A converter (252).

Abstract: An analog-to-digital converter includes an integrator to determine an integrated signal from a communication signal. A comparator quantizes the integrated signal to produce a quantized signal. An adjustable delay element provides a delayed quantized signal to the comparator.

Abstract: A variable gain analog amplifier is described that uses pulse-density modulation in the form of a sigma-delta modulator (SDM) to produce a gain by modulating the selection of a switch that selects the amount of resistance in a negative feedback loop of the amplifier. The output of the SDM is dithered to increase the gain resolution of the analog amplifier, wherein the increased resolution produces a quiet, inaudible transition between changes in gain setting at an output of the variable gain amplifier and in addition produces a quiet, inaudible mixing and merging of audio signals..

Abstract: A variable gain amplifier device (100) with improved gain resolution is achieved. The device includes a programmable gain amplifier (PGA) (110), an analog-to-digital converter (ADC) (160), an automatic level control (ALC) algorithm means (176), and a delta-sigma modulator (180). The PGA (110) is capable to receive and to amplify an analog input signal (154) to thereby generate an analog output signal (164). The PGA (110) includes an amplifier (160) and a switchable resistor network (120). The ADC (170) is coupled to the PGA (110) and is capable to convert the analog output signal (164) to a digital signal (174). The ALC algorithm means (176) is coupled to the ADC (170) and is capable to generate a control code (178) by processing the digital signal (174). The delta-sigma modulator (186) is coupled to the ALC algorithm means (186) and is capable to generate a pulse-density modulated (PDM) signal (182) by processing the control code (178).

Abstract: A crystal oscillator clock circuit which facilitates switching its output between an internally generated clock signal and an externally generated clock signal. A feedback loop detects the presence of an externally generated clock signal applied to an output pin of a crystal oscillator circuit and powers down the internally generated clock signal. As a result, the crystal oscillator clock circuit simply passes the externally generated clock signal as its output signal.

Abstract: A summing-tracking quantizer additively combines multiple feed-forward outputs of cascaded integrator stages of a sigma-delta analog-to-digital converter with a scaled sampled analog signal, and a delayed scaled analog input signal. The summing tracking quantizer compensates for loop delay within a sigma-delta analog-to-digital converter. A loop delay compensation digital-to-analog converter for a sigma-delta analog-to-digital converter is merged with the voltage reference generator within the summing-tracking quantizer. The summing tracking quantizer selects reference voltages from the voltage reference generator based on a previous digital output code. The summing-tracking quantizer has a matrix switch that receives the previous digital output code and selects the reference voltage for applying to comparators for determining a differential quantization code that is additively combined to the previous digital output code to determine the present digital output code.

Abstract: An audio device (200) includes a first and second ICs (210) and (250) and a substrate (205). The first IC includes a sigma-delta, A/D converter (218) operable to convert an analog signal (234) into a pulse density modulated signal (236). A pulse density width modulator encoder (222) is operable to encode the PDM signal into a PDWM signal (244). The PDWM has short and long pulse widths defining first and second bit levels. The leading edges of each pulse bounds each pulse period. The second IC (250) includes a means (254) to receive the PDWM signal, an edge detector (304) operable to detect the leading pulse edges of the PDWM signal, a time-averaging circuit (308) operable to calculate each pulse period from the leading pulse edges and to generate a sample pulse (120) at near the midpoint of each pulse period, and a latch (312) operable to sample and hold the PDWM signal at the sample pulse to decode a PDM signal (278).

Abstract: A variable gain amplifier device (100) with improved gain resolution is achieved. The device includes a programmable gain amplifier (PGA) (110), an analog-to-digital converter (ADC) (160), an automatic level control (ALC) algorithm means (176), and a delta-sigma modulator (180). The PGA (110) is capable to receive and to amplify an analog input signal (154) to thereby generate an analog output signal (164). The PGA (110) includes an amplifier (160) and a switchable resistor network (120). The ADC (170) is coupled to the PGA (110) and is capable to convert the analog output signal (164) to a digital signal (174). The ALC algorithm means (176) is coupled to the ADC (170) and is capable to generate a control code (178) by processing the digital signal (174). The delta-sigma modulator (186) is coupled to the ALC algorithm means (186) and is capable to generate a pulse-density modulated (PDM) signal (182) by processing the control code (178).

Abstract: An audio device (200) includes a first and second ICs (210) and (250) and a substrate (205). The first IC includes a sigma-delta, A/D converter (218) operable to convert an analog signal (234) into a pulse density modulated signal (236). A pulse density width modulator encoder (222) is operable to encode the PDM signal into a PDWM signal (244). The PDWM has short and long pulse widths defining first and second bit levels. The leading edges of each pulse bounds each pulse period. The second IC (250) includes a means (254) to receive the PDWM signal, an edge detector (304) operable to detect the leading pulse edges of the PDWM signal, a time-averaging circuit (308) operable to calculate each pulse period from the leading pulse edges and to generate a sample pulse (120) at near the midpoint of each pulse period, and a latch (312) operable to sample and hold the PDWM signal at the sample pulse to decode a PDM signal (278).

Abstract: A digital active noise cancellation circuit device (330) includes an oversampled, sigma-delta, A/D converter (204), a digital decimation filter (208), a digital intermediate filter (308), a digital interpolation filter (232), and a sigma-delta, D/A converter (252).

Abstract: A summing-tracking quantizer additively combines multiple feed-forward outputs of cascaded integrator stages of a sigma-delta analog-to-digital converter with a scaled sampled analog signal, and a delayed scaled analog input signal. The summing tracking quantizer compensates for loop delay within a sigma-delta analog-to-digital converter. A loop delay compensation digital-to-analog converter for a sigma-delta analog-to-digital converter is merged with the voltage reference generator within the summing-tracking quantizer. The summing tracking quantizer selects reference voltages from the voltage reference generator based on a previous digital output code. The summing-tracking quantizer has a matrix switch that receives the previous digital output code and selects the reference voltage for applying to comparators for determining a differential quantization code that is additively combined to the previous digital output code to determine the present digital output code.

Abstract: A crystal oscillator clock circuit which facilitates switching its output between an internally generated clock signal and an externally generated clock signal. A feedback loop detects the presence of an externally generated clock signal applied to an output pin of a crystal oscillator circuit and powers down the internally generated clock signal. As a result, the crystal oscillator clock circuit simply passes the externally generated clock signal as its output signal.

Abstract: A fractional-n frequency divider that overcomes the presence of so-called dead zones in known frequency divider circuits, n divider cells (3) are connected so as to form a ripple counter (n being an integer greater than or equal to two) and an output multiplexer (22) is provided with a clock signal (24) and an inverted clock signal (25) by the nth divider cell. A polarity circuit (26) generates a polarity signal (23) which clocks the output multiplexer (22) so as to controllably combine the clock signal and the inverted clock signal to produce an output signal (5). A toggle signal (9) toggles between a first and a second integer division configuration so as to provide for fractional divisional outputs therebetween. With n ? divider cells (3) the division ratio therefore can take any fractional value that satisfies the following inequality 2 (n?1) less than or equal to division ratio less than or equal to 2 (n+1)?1.