Abstract: A component carrier includes: i) a first layer stack (comprising at least one first electrically conductive layer structure and/or at least one first electrically insulating layer structure, ii) a component embedded in the first layer stack, where a main surface of the component is essentially flush with an outer main surface of the first layer stack iii) a second layer stack comprising at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure, and iv) a thermally conductive block embedded in the second layer stack. The layer stacks are connected with each other so that a thermal path from the embedded component via the thermally conductive block up to an exterior surface of the component carrier has a minimum thermal conductivity of at least 7 W/mK, in particular at least 40 W/mK. Further, a method of manufacturing the component carrier is described.

Abstract: A component carrier includes i) a first layer stack having a first electrically conductive layer structure and/or at least one first electrically insulating layer structure, ii) a component embedded in the first layer stack, iii) a second layer stack having at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure, and iv) a thermally conductive block embedded in the second layer stack. Hereby, the first layer stack and the second layer stack are connected with each other so that a thermal path from the embedded component via the thermally conductive block up to an exterior surface of the component carrier has a minimum thermal conductivity of at least 7 W/mK, in particular at least 40 W/mK. Further, a method of manufacturing the component carrier is described.

Abstract: A component carrier which includes a stack having at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a recess being at least partially formed in the stack, optionally having an electrically conductive coating, and being configured as waveguide, wherein a plurality of edges delimiting the recess are formed by electrically conductive material of the at least one electrically conductive layer structure and/or of the optional electrically conductive coating.

Abstract: A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and a microwave structure embedded at least partially in the stack. The microwave structure configured for exciting a microwave propagation mode and having at least two stack pieces being interconnected with each other at an electrically conductive connection interface.

Abstract: A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. The at least one electrically conductive layer structure includes a first trace. A tapering trench is formed in the at least one electrically insulating layer structure beside and below the first trace. A method of manufacturing the component carrier is also described.

Abstract: An electronic device and a method for manufacturing such an electronic device are described. The electronic device includes an electronic component, and a component carrier in which the electronic component is embedded. The component carrier includes a first component carrier part having a first cut-out portion and a second component carrier part having a second cut-out portion, the first cut-out portion and the second cut-out portion facing opposite main surfaces of the electronic component. An electrically conductive material is provided on the surface of the first cut-out portion and on the surface of the second cut-out portion. The first cut-out portion and the second cut-out portion respectively form a first cavity and a second cavity on opposite sides of the electronic component.

Abstract: A component carrier which includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a high-frequency component embedded in the stack. At least one waveguide is integrated in the stack. A transmission line and a coupling element configured transmit a signal between the high-frequency component and the at least one waveguide. A transmission and/or reception unit wirelessly transmits and/or receives one or more signals.

Abstract: A drive device includes a component carrier with a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and a cavity formed in the stack. A driven body is arranged at least partially in the cavity and configured for being drivable to move relative to the component carrier. At least one drive coil for creating a magnetic drive field and at least one drive magnet interacts with the magnetic drive field created by the at least one drive coil to generate a force for moving the driven body relative to the component carrier. One of the at least one drive magnet and the at least one drive coil forms part of the component carrier and the other one of the at least one drive magnet and the at least one drive coil forms part of the driven body.

Abstract: A component carrier includes a first stack having at least one first electrically insulating layer structure and at least one first electrically conductive layer structure, and a second stack with at least one second electrically insulating layer structure and at least one second electrically conductive layer structure. The first stack and the second stack are connected with each other so that a vertical two-dimensional electrically conductive connection is established. The first stack has a first cavity and the second stack has a second cavity, the first cavity and the second cavity being separated by at least one further electrically insulating layer structure. At least one of the first cavity and the second cavity is delimited by a wall being at least partially lined with an electrically conductive coating.

Abstract: A component carrier with a first stack and a second stack. The first stack includes at least one first electrically insulating layer structure and at least one first electrically conductive layer structure having a first connection body with a first exposed planar electrically conductive surface. The second stack includes at least one second electrically insulating layer structure and at least one second electrically conductive layer structure having a second connection body with a second exposed planar electrically conductive surface. The first stack and the second stack are connected with each other so that the first exposed planar electrically conductive surface and the second exposed planar electrically conductive surface are connected to establish a vertical two-dimensional electrically conductive connection.

Abstract: A component carrier includes i) a first layer stack having a first electrically conductive layer structure and/or at least one first electrically insulating layer structure, ii) a component embedded in the first layer stack, iii) a second layer stack having at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure, and iv) a thermally conductive block embedded in the second layer stack. Hereby, the first layer stack and the second layer stack are connected with each other so that a thermal path from the embedded component via the thermally conductive block up to an exterior surface of the component carrier has a minimum thermal conductivity of at least 7 W/mK, in particular at least 40 W/mK. Further, a method of manufacturing the component carrier is described.

Abstract: An electronic device and a method for manufacturing such an electronic device are described. The electronic device includes an electronic component, and a component carrier in which the electronic component is embedded. The component carrier includes a first component carrier part having a first cut-out portion and a second component carrier part having a second cut-out portion, the first cut-out portion and the second cut-out portion facing opposite main surfaces of the electronic component. An electrically conductive material is provided on the surface of the first cut-out portion and on the surface of the second cut-out portion. The first cut-out portion and the second cut-out portion respectively form a first cavity and a second cavity on opposite sides of the electronic component.

Abstract: A component carrier with a first stack and a second stack. The first stack includes at least one first electrically insulating layer structure and at least one first electrically conductive layer structure having a first connection body with a first exposed planar electrically conductive surface. The second stack includes at least one second electrically insulating layer structure and at least one second electrically conductive layer structure having a second connection body with a second exposed planar electrically conductive surface. The first stack and the second stack are connected with each other so that the first exposed planar electrically conductive surface and the second exposed planar electrically conductive surface are connected to establish a vertical two-dimensional electrically conductive connection.

Abstract: An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.

Abstract: M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0?n ?N?1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift T? is calculated by ? i = 0 M - 1 ? ? Idx ? ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.

Abstract: An electrical test circuit is disclosed. In one embodiment, the electrical test circuit includes a first input for receiving a test signal of an integrated circuit, a second input for receiving a control signal and a third input for receiving a normalized reference signal, particularly one that is formed to be synchronous with the test signal. Using a control device of the electrical test circuit, the deviation and/or the amplitude and/or the phase of the reference signal and/or of the test signal can be varied. A measuring device generates, by subtracting the reference signal from the test signal, a difference signal which is output via an output.

Abstract: A test apparatus for testing digitized test responses has a generator and a signal extractor. The generator uses direct digital synthesis to generate a set of n digital reference signals which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor contains a test input and reference inputs. The test input receives a digitized test response and the reference inputs are connected to the reference signals which are generated by the generator. The signal extractor generates scalar products from a respective reference signal and the test response and uses the products to calculate whether a combination of reference signals is contained in the test response.

Abstract: An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

Abstract: A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency fs at its output. A phase modulator generates a test clock subjected to jitter and having the clock frequency ft at its output. The output of the data pattern generator is connected to a terminal for connection to a data input of a semiconductor component to be tested. The output of the phase modulator is connected to a terminal for connection to a clock input of a semiconductor component to be tested. An evaluation device determines the jitter parameters of the input signal at the input of the data device from the low-frequency component of the input signal. In this case, the low-frequency component contains only frequency components of frequencies which are less than half the sampling frequency fs/2.

Abstract: An electric tolerance analysis circuit for digital and digitized measured values has inputs for receiving a measured value, a reference value, and a tolerance value and also an output for transmitting an output value. The electric tolerance analysis circuit also has a checking device for checking the measured value using at least one prescribable tolerance criterion and has an output device for outputting an output value which is obtained from the state of the checking device, depending on whether or not the measured value meets the respective prescribed tolerance criterion.