Patents by Inventor Sebastian T. Ventrone
Sebastian T. Ventrone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140201579Abstract: Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays. The finite state machines are sensitive to a predetermined sequence of addresses sent to the memory array or the time between a series of memory array errors detected by an error detection circuit. Upon detection of the pre-set addresses or errors the finite state machines either (i) enable or disable specific circuit functions or (ii) disrupt the operation of the integrated circuit.Type: ApplicationFiled: January 16, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Igor Arsovski, Sebastian T. Ventrone
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Publication number: 20140195771Abstract: In a particular embodiment, a method of anticipatorily loading a page of memory is provided. The method may include, during execution of first program code using a first page of memory, collecting data for at least one attribute of the first page of memory, including collecting data about at least one next page of memory that interacts with the first page of memory for a historical topology attribute of the first page of memory. The method may also include, during execution of second program code using the first page of memory, determining a second page of memory to anticipatorily load based on the historical topology attribute of the first page of memory.Type: ApplicationFiled: January 4, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Paul A Niekrewicz, Aydin Suren, Sebastian T. Ventrone
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Patent number: 8756549Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.Type: GrantFiled: January 5, 2011Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Richard S. Graf, Keishi Okamoto, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
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Patent number: 8612815Abstract: Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.Type: GrantFiled: December 16, 2011Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
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Publication number: 20130325156Abstract: Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: International Business Machines CorporationInventors: Casey J. Grant, Kurt A. Tallman, Sebastian T. Ventrone
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Patent number: 8575964Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.Type: GrantFiled: March 22, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, John Sargis, Jr., Sebastian T. Ventrone, Charles S. Woodruff
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Publication number: 20130259488Abstract: A reactive metal optical security device for implementation in an optical network and/or system to provide a mechanism for disrupting the optical network and/or system. The security device includes a mirror comprising a reactive metal stack and configured to reflect an optical signal and receive an electrical signal. The security device further includes a semiconductor chip configured to send the electrical signal to the mirror.Type: ApplicationFiled: March 28, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry BERNSTEIN, Kenneth J. GOODNOW, Clarence R. OGILVIE, Charles S. WOODRUFF, Sebastian T. VENTRONE
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Publication number: 20130249596Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.Type: ApplicationFiled: March 22, 2012Publication date: September 26, 2013Applicant: International Business Machines CorporationInventors: Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, John Sargis, JR., Sebastian T. Ventrone, Charles S. Woodruff
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Patent number: 8499140Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.Type: GrantFiled: December 14, 2011Date of Patent: July 30, 2013Assignee: International Business Machines CorporationInventors: Susan K. Lichtensteiger, Pascal A. Nsame, Sebastian T. Ventrone
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Publication number: 20130181838Abstract: Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: International Business Machines CorporationInventors: Shawn M. Luke, Michael R. Ouellette, Karl V. Swanke, Sebastian T. Ventrone
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Publication number: 20130159803Abstract: Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: International Business Machines CorporationInventors: Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
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Patent number: 8424071Abstract: In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.Type: GrantFiled: November 19, 2009Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Mariette Awad, Deanna C. Lim, Pascal A. Nsame, Daneyand J. Singley, Sebastian T. Ventrone
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Publication number: 20130074033Abstract: System and computer-implemented methods herein design a configurable pipelined processor. Such systems and methods provide a configuration specification, by providing a base processor or digital design description, a base instruction set with a plurality of base instructions, and a plurality of configurable features. At least one of the configurable features is an additional instruction different from the base instructions. Further, such systems and methods generate a hardware implementation based on the configuration specification to produce a plurality of configured pipeline stages. The configured pipeline stages are different from base pipeline stages in a base processor or digital design hardware implementation (corresponding to the base processor or digital design description as a result of the additional instruction being included in the configuration specification).Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Applicant: International Business Machines CorporationInventors: Ezra D. HALL, Paul A. NIEKREWICZ, Rohit SHETTY, Aydin SUREN, Sebastian T. VENTRONE
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Patent number: 8341428Abstract: A system and method for protecting computing systems, and more particularly a system and method which a dedicated hardware component configured to communicate with a protection program. A computer hardware subsystem includes a memory comprising content. The content is at least a list of files which have been modified within a predetermined period of time. The list of files is a subset of files of a hard drive. A dedicated hardware component is configured to track the files which have been modified and provide a location of the files to the memory. A communication link between the dedicated hardware component and a protection program provides the protection program with the subset of files of the hard drive as referenced by the memory content.Type: GrantFiled: June 25, 2007Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Elie Awad, Mariette Awad, Adam E. Trojanowski, Sebastian T. Ventrone
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Patent number: 8302037Abstract: A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.Type: GrantFiled: June 30, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony R Bonaccio, Hayden (Clay) Cranford, Jr., Joseph A Iadanza, Pradeep Thiagarajan, Sebastian T Ventrone, Benjamin T Voegeli
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Patent number: 8279861Abstract: A computer-implemented method and system of enabling concurrent real-time multi-language communication between multiple participants using a selective broadcast protocol, the method including receiving at a first server a real-time communication from a first participant, the real-time communication being addressed to a second participant constructed in a first spoken language. A preferred spoken language of receipt of real-time communication is identified by the second participant. A determination is made whether the preferred spoken language of receipt is different than that of the first spoken language of the real-time communication.Type: GrantFiled: December 8, 2009Date of Patent: October 2, 2012Assignee: International Business Machines CorporationInventors: Chi-Chuen Chao-Suren, Ezran D. B. Hall, Pascal A. Nsame, Aydin Suren, Sebastian T. Ventrone
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Patent number: 8239811Abstract: Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.Type: GrantFiled: March 24, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Theodoros E. Anemikos, Phillip L. Corson, Mete Erturk, Ezra D. B. Hall, Anthony J. Perri, Sebastian T. Ventrone
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Patent number: 8239791Abstract: Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.Type: GrantFiled: June 9, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Susan K. Lichtensteiger, Michael R. Ouellette, Raymond W. M. Schuppe, Sebastian T. Ventrone
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Publication number: 20120168416Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.Type: ApplicationFiled: January 5, 2011Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Richard S. Graf, Keishi Okamoto, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
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Patent number: 8200987Abstract: A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.Type: GrantFiled: August 25, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: John E. Campbell, William T. Devine, Sebastian T. Ventrone