Patents by Inventor Sebastian Theodore Ventrone
Sebastian Theodore Ventrone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10197730Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical via connections in chip-to-chip transmission in a 3D chip stack structure using an optical via, and methods of manufacture. The structure has a first wafer, including a first waveguide coupled to an optical resonator in the first wafer, and a second wafer, including a second waveguide, located over the first wafer. The structure also includes an optical via extending between the optical resonator of the first wafer and the second waveguide of the second wafer to optically couple the first and second waveguides.Type: GrantFiled: November 8, 2017Date of Patent: February 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Yves T. Ngu, Vibhor Jain, John J. Ellis-Monaghan, Sebastian Theodore Ventrone, Saurabh Sirohi
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Patent number: 8793365Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.Type: GrantFiled: March 4, 2009Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony Richard Bonaccio, Hayden C. Cranford, Jr., Alfred Degbotse, Joseph Andrew Iadanza, Todd Edwin Leonard, Pradeep Thiagarajan, Sebastian Theodore Ventrone
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Patent number: 8037337Abstract: A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: GrantFiled: November 28, 2007Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Patent number: 7831935Abstract: A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.Type: GrantFiled: August 29, 2007Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Kenneth Joseph Goodnow, Clarence Rosser Ogilvie, Keith Robert Williams, Sebastian Theodore Ventrone
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Publication number: 20100228861Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.Type: ApplicationFiled: March 4, 2009Publication date: September 9, 2010Applicant: International Business Machines CorporationInventors: Igor Arsovski, Anthony Richard Bonaccio, Hayden C. Cranford, JR., Alfred Degbotse, Joseph Andrew Iadanza, Todd Edwin Leonard, Pradeep Thiagarajan, Sebastian Theodore Ventrone
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Patent number: 7715995Abstract: An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.Type: GrantFiled: March 12, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Kenneth Joseph Goodnow, Clarence Rosser Ogilvie, Nitin Sharma, Sebastian Theodore Ventrone, Charles S. Woodruff
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Publication number: 20090153324Abstract: An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.Type: ApplicationFiled: March 12, 2008Publication date: June 18, 2009Inventors: Kenneth Joseph Goodnow, Clarence Rosser Ogilvie, Nitin Sharma, Sebastian Theodore Ventrone, Charles S. Woodruff
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Publication number: 20090157334Abstract: An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.Type: ApplicationFiled: December 14, 2007Publication date: June 18, 2009Inventors: Kenneth Joseph Goodnow, Clarence Rosser Ogilvie, Nitin Sharma, Sebastian Theodore Ventrone, Charles S. Woodruff
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Publication number: 20090138676Abstract: A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Inventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Patent number: 7463083Abstract: A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: GrantFiled: November 9, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Patent number: 7454642Abstract: A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.Type: GrantFiled: March 31, 2006Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Kenneth Joseph Goodnow, Clarence Rosser Ogilvie, Keith Robert Williams, Sebastian Theodore Ventrone
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Patent number: 7317348Abstract: A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.Type: GrantFiled: January 27, 2006Date of Patent: January 8, 2008Assignee: International Business Machines CorporationInventors: Nancy H. Pratt, Sebastian Theodore Ventrone
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Patent number: 7135907Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.Type: GrantFiled: October 21, 2005Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Anthony Richard Bonaccio, John Maxwell Cohn, Alvar Antonio Dean, Amir H. Farrahi, David J. Hathaway, Sebastian Theodore Ventrone
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Patent number: 7080344Abstract: A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect's type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.Type: GrantFiled: June 25, 2003Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Stanislav Peter Bajuk, Jack Robert Smith, Sebastian Theodore Ventrone
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Patent number: 7071757Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.Type: GrantFiled: September 6, 2001Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Anthony Richard Bonaccio, John Maxwell Cohn, Alvar Antonio Dean, Amir H. Farrahi, David J. Hathaway, Sebastian Theodore Ventrone
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Patent number: 6944698Abstract: A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history table. In response to bus request made by the cores, the common bus is arbitrated according to information stored in the bus request history table by an arbiter.Type: GrantFiled: July 8, 2002Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventors: W. Riyon Harding, Thomas Michael Lepsic, Sebastian Theodore Ventrone
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Patent number: 6934656Abstract: A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.Type: GrantFiled: November 4, 2003Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: Jason Michael Norman, Nancy H. Pratt, Sebastian Theodore Ventrone
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Publication number: 20040268288Abstract: A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect“s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.Type: ApplicationFiled: June 25, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stanislav Peter Bajuk, Jack Robert Smith, Sebastian Theodore Ventrone
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Patent number: 6834353Abstract: In a first aspect, a method is provided for conserving power in a processing integrated circuit. The method includes the steps of (1) calculating power consumption for executing an instruction and data corresponding to the instruction; and (2) executing the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of (1) comparing a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and (2) if the total power exceeds the power budget, freezing execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution was frozen. Numerous other aspects are provided, as are systems and apparatus.Type: GrantFiled: October 22, 2001Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Jack Robert Smith, Sebastian Theodore Ventrone
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Patent number: 6820254Abstract: A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in communication with the CPU and the system memory. Control logic within the code-optimizing coprocessor causes the code-optimizing coprocessor to generate optimized code from the legacy code at the same time the CPU executes the legacy code, such that the optimized code is tailored according to the CPU. After the code-optimizing coprocessor has generated at least some optimized code, the code-optimizing coprocessor causes the CPU to automatically utilize at least some optimized code in lieu of at least some of the legacy code.Type: GrantFiled: March 19, 2001Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Jack Robert Smith, Sebastian Theodore Ventrone