Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

Abstract: A processing system includes one or more processing units, a memory including a protected region, and a hardware security module. The hardware security module is configured to selectively modify a page table stored in the protected region of the memory in response to write or modify requests from the at least one processing unit. In some variations, the hardware security module can modify the page table in response to verifying that a security criterion is met by the requested modification of the page table. The hardware security module can also access a code signature in response to a request to mark a page in the page table as eligible for execution and selectively mark the page as executable based on whether the code signature matches a signature of code stored in the page.

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: A video device having data lanes and a method of operating the video device includes generating performance monitoring and/or debug data in response to the operation of the video device. The generated data is sampled from component of the video device operating in various clocking domain. The data sampled from the components is combined into a unified stream which is independent of the various clocking domain. The unified stream is transmitted across one more data lanes of a video link along with corresponding audio and/or video data in real time.

Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

Abstract: Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.

Abstract: A method resumes an accelerated processing device (APD) wavefront in which a subset of elements have faulted. A restore command for a job including a wavefront is received. A list of context states for the wavefront is read from a memory associated with a APD. An empty shell wavefront is created for restoring the list of context states. A portion of not acknowledged data is masked over a portion of acknowledged data within the restored wavefronts.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on a accelerated processing device. Embodiments include, detecting by an accelerated processing device a memory exception, and preempting a process from running on the accelerated processing device based upon the detected exception.

Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device.

Abstract: A method of controlling voltage in a circuit is provided. Within the circuit, a block of an electrical component provides an indication that it desires to switch states (such as from off to on, on to off, or from one speed to another). The change in states requires a different current draw by the electrical component block. The indication is received by an electrical component that controls the voltage of the circuit. The electrical component that controls the voltage then issues a signal granting permission for the electrical component block to switch states. This permission signal is received by the electrical component and the electrical component block changes state.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: Embodiments describe herein provide a method of for managing task scheduling on a accelerated processing device. The method includes executing a first task within the accelerated processing device (APD), monitoring for an interruption of the execution of the first task, and switching to a second task when an interruption is detected.

Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

Abstract: A method and device for setting a processor performance profile for a processor that is unable to directly measure voltage supplied by a voltage regulator includes determining a voltage requested of the voltage regulator and determining a first characteristic of a first portion of the electrical component. The first characteristic is one of power consumed by the first portion of the electrical component and load presented by the first portion of the electrical component. A first current is then determined by using the first voltage, the first characteristic, and a known relationship therebetween. A third voltage that is an estimate of the voltage supplied by the voltage regulator is then determined by comparing the first current to load line characteristics of the electrical component. The third voltage is then used to manage performance of the processor.

Abstract: The desire to use an Accelerated Processing Device (APD) for general computation has increased due to the APD's exemplary performance characteristics. However, current systems incur high overhead when dispatching work to the APD because a process cannot be efficiently identified or preempted. The occupying of the APD by a rogue process for arbitrary amounts of time can prevent the effective utilization of the available system capacity and can reduce the processing progress of the system. Embodiments described herein can overcome this deficiency by enabling the system software to pre-empt a process executing on the APD for any reason. The APD provides an interface for initiating such a pre-emption. This interface exposes an urgency of the request which determines whether the process being preempted is allowed a grace period to complete its issued work before being forced off the hardware.