Patents by Inventor Sei Yamagishi

Sei Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Allocating plurality of RAMs to FPGA block RAM
    Patent number: 9971860
    Abstract: A design apparatus includes a processing unit configured to allocate a plurality of RAMs to a FPGA block RAM in at least one of a word direction and a bit direction thereof, and to generate a description, in a hardware description language, of a control circuit that controls input and output signals of each of the plurality of RAMs so as to allow each of the plurality of RAMs to be accessed as a single RAM.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 15, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Sei Yamagishi, Masataka Mine
  • DESIGN APPARATUS, COMPUTER-READABLE MEDIUM, AND FPGA-BASED DESIGN METHOD
    Publication number: 20160292337
    Abstract: A design apparatus includes a processing unit configured to allocate a plurality of RAMs to a FPGA block RAM in at least one of a word direction and a bit direction thereof, and to generate a description, in a hardware description language, of a control circuit that controls input and output signals of each of the plurality of RAMs so as to allow each of the plurality of RAMs to be accessed as a single RAM.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 6, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Sei Yamagishi, Masataka Mine