Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

Abstract: During a training procedure for communicating via a full-duplex communication link, a first communication device receives training information from a second communication device. The training information corresponds to first signal processing parameters developed at the second communication device for use by the second communication device to process signals received by the second communication device via the full-duplex communication link. After receiving the training information from the second communication device, the first communication device develops second signal processing parameters to be used by the first communication device to process signals received by the first communication device via the full-duplex communication link. The second signal processing parameters are developed using the training information received from the second communication device.

Abstract: A link between a PHY device and a link partner is established by performing link training. If the link becomes at least partially inoperable, a first fast retrain technique is executed. A signature indicating that the first fast retrain technique successfully began but failed during execution before completion of the first fast retrain technique is received at the PHY device. In response to receiving the signature, a second fast retrain technique is executed.

Abstract: A method of operation for an Ethernet transceiver is disclosed. The method includes receiving, with receiver circuitry from a link partner transceiver, a data signal carrying data. A threshold change in signal quality of the data signal is detected. A fast retrain operation is initiated in response to the threshold change in signal quality. The fast retrain operation includes adaptively self-updating the receiver circuitry based on filter information generated by the receiver circuitry independently of signals received from the link partner transceiver.

Abstract: A transmitter transmits a first signal via a first cable at a first baud rate. A receiver receives a second signal via the first cable concurrently with transmitting the first signal via the first cable. The second signal is transmitted by another device at a second baud. rate that is lower than both i) the first baud rate and ii) a third baud rate at which a third signal is being transmitted in a second cable that causes crosstalk in the second signal being received via the first cable. Reception of the second signal at the second baud rate that is lower than the third baud rate facilitates mitigation of the crosstalk in the second signal caused by transmission of the third signal in the second cable at the third baud rate.

Abstract: A physical layer transceiver, for connecting a host device to a wireline channel medium that is divided into a total number of link segments, includes a host interface for coupling to a host device, a line interface for coupling to the wireline channel medium, and feed-forward equalization (FFE) circuitry operatively coupled to the line interface to add back, into a signal, components that were scattered in time. Respective individual filter segments are selectably configurable, by adjustment of respective delay lines, to correspond to respective individual link segments. The FFE circuitry also includes control circuitry configured to detect a signal energy peak in at least one particular link segment and, upon detection of the signal energy peak in the particular link segment, configure a respective one of the respective individual filter segments, by adjustment of a respective delay line, to correspond to the respective particular link segment.

Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

Abstract: A physical layer transceiver for a serial data channel includes receiver circuitry having a local clock. Received signals arrive on the channel according to a remote clock. Clock-data recovery circuitry aligns the local clock with the remote clock by correcting phase and frequency error between the local and remote clocks. The clock-data recovery circuitry includes digital phase error detection circuitry operating according to a digital clock to detect phase error between the local and remote clocks, analog phase rotation circuitry to correct the detected phase error, distribution circuitry to divide the detected phase error into multiple phase error steps, and an analog clock source configured to provide the local clock to the analog phase rotation circuitry, and to provide to the distribution circuitry a distribution clock that is slower than the local clock, to correct the local clock by at least one step during one digital clock period.

Abstract: A method of operation for an Ethernet transceiver is disclosed. The method includes entering a training sequence. The training sequence includes transferring uncoded two-level symbols to a link partner; exchanging updated precoder coefficients with the link partner; and directly following exchanging updated precoder coefficients, transferring multi-level symbols to the link partner. The multi-level symbols being encoded consistent with the exchanged updated precoder coefficients and having greater than two symbol levels.

Abstract: A method of operation on an Ethernet network having multiple Ethernet links interconnected via a network device. The method includes detecting installation of a new Ethernet link in the Ethernet network utilizing the network device. A link training process is then initiated for the new Ethernet link. The link training process includes transmitting training data at a first transmit power level and first data rate to a link partner during a data transfer interval. Network feedback information is then accessed, including performance metrics associated with the multiple Ethernet links during the training data transfer interval. The first data rate and/or first transmit power level are then adjusted to an adjusted second data rate and/or second transmit power level based on the network feedback information.

Abstract: A physical layer transceiver, for connecting a host device to a wireline channel medium having a cable length, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface. The filter circuitry includes a plurality of filter segments, fewer in number than a total number of link segments in the cable length. Individual filter segments in the plurality of filter segments are configurable to correspond to individual link segments, and are separately controllable from other filter segments. Control circuitry detects a change of transmission conditions in a particular link segment, and upon detection of the change of transmission conditions, changes a configuration of one of the plurality of filter segments to cause an alteration in filtering of signals in the particular link segment at which the change of transmission conditions is detected.

Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry having receiver circuitry to receive refresh signals during corresponding refresh cycles from a link partner during a low-power idle mode of operation. Each refresh signal has a refresh period, and where a quiet period is interposed between successive refresh cycles. Signal quality detection circuitry, during the low-power idle mode, determines a measure of signal quality associated with the received refresh signals. Subsequent refresh cycles exhibit at least one of an adjusted refresh period or an adjusted quiet period based on the measure of signal quality.

Abstract: A method of operating an Ethernet transceiver includes initializing the Ethernet transceiver during a training mode of operation by monitoring background link operating characteristics with on-chip circuitry during a non-data-transfer interval to establish a baseline alien crosstalk value. Training data is then transmitted at a first transmit power level and first data rate to a link partner during a data transfer interval. The link is monitored with the on-chip circuitry during the data transfer interval to detect feedback indicating alien crosstalk effects to neighboring Ethernet links due to the transmitting. The first data rate and/or first transmit power level is then adjusted to an adjusted second data rate and/or second transmit power level based on the feedback. The Ethernet transceiver is then operated in a normal data transfer mode utilizing the adjusted second data rate and/or transmit power level.

Abstract: A method for fast link recovery for an Ethernet link is disclosed. The method includes detecting a drop in link quality and performing a first fast retrain sequence, including determining and exchanging THP coefficients based on the drop in link quality. If the performed fast retrain fails to recover the link, a data rate associated with the link is reduced, and a second fast retrain sequence performed.

Abstract: A method of operation for an Ethernet transceiver is disclosed. The method includes operating the Ethernet transceiver in a data mode, and triggering a fast retrain sequence of steps based on trickling error information. The triggering includes detecting error information, averaging the detected error information over a time interval to generate the trickling error information, comparing the averaged detected error information to a selected threshold value, and initiating the fast retrain sequence of steps based on the comparing.

Abstract: A method for fast link recovery for an Ethernet link is disclosed. The method includes detecting a drop in link quality and performing a first fast retrain sequence, including determining and exchanging THP coefficients based on the drop in link quality. If the performed fast retrain fails to recover the link, a data rate associated with the link is reduced, and a second fast retrain sequence performed.

Abstract: A method of operating an Ethernet transceiver includes initializing the Ethernet transceiver during a training mode of operation by monitoring background link operating characteristics with on-chip circuitry during a non-data-transfer interval to establish a baseline alien crosstalk value. Training data is then transmitted at a first transmit power level and first data rate to a link partner during a data transfer interval. The link is monitored with the on-chip circuitry during the data transfer interval to detect feedback indicating alien crosstalk effects to neighboring Ethernet links due to the transmitting. The first data rate and/or first transmit power level is then adjusted to an adjusted second data rate and/or second transmit power level based on the feedback. The Ethernet transceiver is then operated in a normal data transfer mode utilizing the adjusted second data rate and/or transmit power level.

Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry having receiver circuitry to receive refresh signals during corresponding refresh cycles from a link partner during a low-power idle mode of operation. Each refresh signal has a refresh period, and where a quiet period is interposed between successive refresh cycles. Signal quality detection circuitry, during the low-power idle mode, determines a measure of signal quality associated with the received refresh signals. Subsequent refresh cycles exhibit at least one of an adjusted refresh period or an adjusted quiet period based on the measure of signal quality.

Abstract: A method of operation for an Ethernet transceiver is disclosed. The method includes receiving, with receiver circuitry from a link partner transceiver, a data signal carrying data. A threshold change in signal quality of the data signal is detected. A fast retrain operation is initiated in response to the threshold change in signal quality. The fast retrain operation includes adaptively self-updating the receiver circuitry based on filter information generated by the receiver circuitry independently of signals received from the link partner transceiver.

Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.