Patents by Inventor Seid Hadi Rasouli
Seid Hadi Rasouli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9972624Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.Type: GrantFiled: August 23, 2013Date of Patent: May 15, 2018Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Publication number: 20180123568Abstract: Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventors: Seid Hadi Rasouli, Xiangdong Chen, Venugopal Boynapalli
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Patent number: 9859891Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.Type: GrantFiled: June 24, 2016Date of Patent: January 2, 2018Assignee: QUALCOMM IncorporatedInventors: Dorav Kumar, Venkatasubramanian Narayanan, Bala Krishna Thalla, Seid Hadi Rasouli, Radhika Vinayak Guttal, Sivakumar Paturi
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Publication number: 20170373689Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: Dorav KUMAR, Venkatasubramanian NARAYANAN, Bala Krishna THALLA, Seid Hadi RASOULI, Radhika Vinayak GUTTAL, Sivakumar PATURI
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Patent number: 9786663Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.Type: GrantFiled: August 23, 2013Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Ohsang Kwon
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Publication number: 20170257080Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: Seid Hadi RASOULI, Xiangdong CHEN, Venugopal BOYNAPALLI
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Patent number: 9755618Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.Type: GrantFiled: March 4, 2016Date of Patent: September 5, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Xiangdong Chen, Venugopal Boynapalli
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Publication number: 20170221826Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.Type: ApplicationFiled: April 20, 2017Publication date: August 3, 2017Inventors: Seid Hadi RASOULI, Animesh DATTA, Ohsang KWON
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Patent number: 9673786Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: GrantFiled: April 12, 2013Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Patent number: 9659936Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.Type: GrantFiled: August 23, 2013Date of Patent: May 23, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Ohsang Kwon
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Patent number: 9577635Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ?C, where E is the internal enable node and C is the clock.Type: GrantFiled: January 15, 2015Date of Patent: February 21, 2017Assignee: QUALCOMM INCORPORATEDInventors: Seid Hadi Rasouli, Steven James Dillen, Animesh Datta
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Publication number: 20160211846Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ?C, where E is the internal enable node and C is the clock.Type: ApplicationFiled: January 15, 2015Publication date: July 21, 2016Inventors: Seid Hadi RASOULI, Steven James DILLEN, Animesh DATTA
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Patent number: 9318476Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.Type: GrantFiled: March 3, 2014Date of Patent: April 19, 2016Assignee: QUALCOMM IncorporatedInventors: Xiangdong Chen, Ohsang Kwon, Foua Vang, Animesh Datta, Seid Hadi Rasouli
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Publication number: 20150249076Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.Type: ApplicationFiled: March 3, 2014Publication date: September 3, 2015Applicant: QUALCOMM INCORPORATEDInventors: XIANGDONG CHEN, OHSANG KWON, FOUA VANG, ANIMESH DATTA, SEID HADI RASOULI
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Patent number: 9020084Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.Type: GrantFiled: January 31, 2013Date of Patent: April 28, 2015Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Saravanan Marimuthu, Ohsang Kwon
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Publication number: 20150054567Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: QUALCOMM IncorporatedInventors: Seid Hadi RASOULI, Animesh DATTA, Ohsang KWON
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Publication number: 20150054568Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: QUALCOMM INCORPORATEDInventors: Seid Hadi RASOULI, Michael Joseph BRUNOLLI, Christine Sung-An HAU-RIEGE, Mickael MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON
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Publication number: 20140306735Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: ApplicationFiled: April 12, 2013Publication date: October 16, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Publication number: 20140225655Abstract: Techniques for clock gating a synchronizer are described herein. In one embodiment a circuit for clock gating a synchronizer comprises a clock-gating circuit configured to receive an input clock signal, and to selectively provide either the input clock signal or a fixed clock signal to the synchronizer. The circuit also comprises a comparator configured to compare a data value of a data signal input to the synchronizer, a first value of the synchronizer, and a second value of the synchronizer with one another, to instruct the clock-gating circuit to provide the input clock signal to the synchronizer if the data value, the first value, and the second value are not all the same, and to instruct the clock-gating circuit to provide the fixed clock signal to the synchronizer if the data value, the first value, and the second value are all the same.Type: ApplicationFiled: February 14, 2013Publication date: August 14, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Ohsang Kwon
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Publication number: 20140211893Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Saravanan Marimuthu, Ohsang Kwon