Patents by Inventor Seigo OOSAWA

Seigo OOSAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230093554
    Abstract: A semiconductor device includes a semiconductor element, a sealing material, and an extension wire. The semiconductor element has, on a front surface, a first electrode pad and at least one second electrode pad, and generates a current in a direction connecting the front surface and a back surface. The sealing material is made of an insulating resin material and covers a part of the front surface and a side surface of the semiconductor element. The extension wire is disposed above the semiconductor element and inside the sealing material or on the sealing material. The extension wire is electrically connected to the second electrode pad, and extends from a position inside of a contour of the semiconductor element to a position outside of the contour of the semiconductor element.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 23, 2023
    Inventors: SEIGO OOSAWA, YASUSHI OOKURA
  • Publication number: 20230032353
    Abstract: A semiconductor device includes a semiconductor element, a sealing member, and a rewiring layer. The rewiring layer includes an insulating layer covering a front surface of the semiconductor element and a part of the sealing member, an electrode connected to the semiconductor element, and an externally-exposed layer being conductive and covering a portion of the electrode exposed from the insulating layer.
    Type: Application
    Filed: October 12, 2022
    Publication date: February 2, 2023
    Inventors: TAKAHIRO NAKANO, SEIGO OOSAWA, YASUSHI OOKURA, NAOHITO MIZUNO, YOSHIHIRO INUTSUKA
  • Patent number: 10109727
    Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: October 23, 2018
    Assignee: DENSO CORPORATION
    Inventors: Kazuhiro Oyama, Yasushi Higuchi, Seigo Oosawa, Masaki Matsui, Youngshin Eum
  • Publication number: 20170345919
    Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.
    Type: Application
    Filed: December 8, 2015
    Publication date: November 30, 2017
    Inventors: Kazuhiro OYAMA, Yasushi HIGUCHI, Seigo OOSAWA, Masaki MATSUI, Youngshin EUM
  • Patent number: 9634095
    Abstract: In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: April 25, 2017
    Assignee: DENSO CORPORATION
    Inventors: Seigo Oosawa, Yutaka Tomatsu, Masahiro Ogino, Tomomi Oobayashi
  • Publication number: 20150372090
    Abstract: In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced.
    Type: Application
    Filed: December 23, 2013
    Publication date: December 24, 2015
    Inventors: Seigo OOSAWA, Yutaka TOMATSU, Masahiro OGINO, Tomomi OOBAYASHI
  • Patent number: 9171906
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 27, 2015
    Assignee: DENSO CORPORATION
    Inventors: Eiichi Taketani, Seigo Oosawa
  • Patent number: 9136335
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Eiichi Taketani, Seigo Oosawa
  • Patent number: 8841719
    Abstract: A semiconductor device includes: a semiconductor substrate; an interlayer film on the substrate; a surface electrode on the interlayer film; a surface pad on the surface electrode; a backside electrode on the substrate; an element area including a cell portion having a vertical semiconductor element and a removal portion having multiple contact regions; and an outer periphery area. The surface electrode in the removal portion is electrically coupled with each contact region through a first contact hole in the interlayer film. The surface electrode in the cell portion is electrically coupled with the substrate through a second contact hole in the interlayer film. A part of the surface electrode in the removal portion facing each contact region is defined as a contact portion. The surface electrode includes multiple notches on a shortest distance line segment between each contact portion and the surface pad.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: September 23, 2014
    Assignee: DENSO CORPORATION
    Inventors: Seigo Oosawa, Shoji Mizuno, Yutaka Tomatsu
  • Publication number: 20140246718
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Applicant: DENSO CORPORATION
    Inventors: Eiichi TAKETANI, Seigo OOSAWA
  • Publication number: 20120261714
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 18, 2012
    Applicant: DENSO CORPORATION
    Inventors: Eiichi TAKETANI, Seigo Oosawa
  • Publication number: 20120199900
    Abstract: A semiconductor device includes: a semiconductor substrate; an interlayer film on the substrate; a surface electrode on the interlayer film; a surface pad on the surface electrode; a backside electrode on the substrate; an element area including a cell portion having a vertical semiconductor element and a removal portion having multiple contact regions; and an outer periphery area. The surface electrode in the removal portion is electrically coupled with each contact region through a first contact hole in the interlayer film. The surface electrode in the cell portion is electrically coupled with the substrate through a second contact hole in the interlayer film. A part of the surface electrode in the removal portion facing each contact region is defined as a contact portion. The surface electrode includes multiple notches on a shortest distance line segment between each contact portion and the surface pad.
    Type: Application
    Filed: January 10, 2012
    Publication date: August 9, 2012
    Applicant: DENSO CORPORATION
    Inventors: Seigo OOSAWA, Shoji MIZUNO, Yutaka TOMATSU