Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Abstract: A semiconductor system includes a data storage unit including memory blocks, a circuit group and a control circuit, wherein the memory blocks store data therein and are arranged in a longitudinal direction and a vertical direction. The circuit group is suitable for performing a program, read or erase operation on the memory blocks, and the control circuit controls the circuit group. A memory control unit is suitable for controlling the data storage unit, wherein each of the memory blocks includes a plurality of sub-memory blocks. The sub-memory blocks arranged in the longitudinal direction share bit lines and do not share word lines and source lines. Further, the sub-memory arranged in the vertical direction share the bit lines or the source lines.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory strings coupled between the bit lines and a second common source line formed over the bit lines, wherein each of the bit lines includes a stacked structure of a conductive layer and a silicon layer formed on the conductive layer.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.

Abstract: A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.

Abstract: A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory strings coupled between the bit lines and a second common source line formed over the bit lines, wherein each of the bit lines includes a stacked structure of a conductive layer and a silicon layer formed on the conductive layer.

Abstract: A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.

Abstract: A non-volatile memory device according to an embodiment of the present invention includes a first memory layer including a plurality of memory cells stacked between a first conductive line and a second conductive line over a semiconductor substrate. In addition, a second memory layer including the plurality of memory cells stacked between the second conductive line and a third conductive line. Further, the second memory layer is extended over the page buffer and the peripheral circuit sequentially arranged from the first memory layer.

Abstract: A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.

Abstract: A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor coupled to an odd drain selection line or an even drain selection line, memory cells coupled to word lines, and a source selection transistor coupled to an odd source selection line or an even source selection line, page buffers suitable for storing data, a selection switch unit suitable for transferring the data stored in the page buffers or various voltages supplied from an external source to the bit lines and the source lines; and a control circuit suitable for controlling the page buffers and the selection switch unit.

Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Abstract: A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

Abstract: A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Abstract: A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.

Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.

Abstract: A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers on a substrate, first vertical lines suitable for coupling bit lines, and second vertical lines suitable for coupling word lines of the memory blocks vertically stacked, wherein the memory blocks include selection lines vertically stacked and separated from each other, and the bit lines are coupled to the memory blocks and arranged in a plurality of layers.

Abstract: A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor coupled to an odd drain selection line or an even drain selection line, memory cells coupled to word lines, and a source selection transistor coupled to an odd source selection line or an even source selection line, page buffers suitable for storing data, a selection switch unit suitable for transferring the data stored in the page buffers or various voltages supplied from an external source to the bit lines and the source lines; and a control circuit suitable for controlling the page buffers and the selection switch unit.