Abstract: A data transfer unit (13) is provided for use in a clock swapping system which controls data transfer with a data transmission permit signal (rwo) and data reception permit signal (rro). The data transfer unit (13) includes a data latch (21) which latches transfer data in time with a transmission enable signal (ewi) and from which the data is read in time with a reception enable signal (eri), a first FR-FF circuit (31) which delays the transmission enable signal (ewi) for at least one period of a transmission clock (ckw), and a third SR-FF circuit 33 which delays the reception enable signal (eri) for a period of a reception clock (ckr). In the data transfer unit (13), a signal latched by the first SR-FF circuit (31) is latched a series of two times in time with the reception clock (ckr) to generate the reception permit signal (rro) and a signal latched by the third SR-FF circuit (33) is latched a series of two times in time with the transmission clock (ckw) to generate the transmission permit signal (rwo).

Abstract: A data transfer unit (13) is provided for use in a clock swapping system which controls data transfer with a data transmission permit signal (rwo) and data reception permit signal (rro). The data transfer unit (13) includes a data latch (21) which latches transfer data in time with a transmission enable signal (ewi) and from which the data is read in time with a reception enable signal (eri), a first FR-FF circuit (31) which delays the transmission enable signal (ewi) for at least one period of a transmission clock (ckw), and a third SR-FF circuit 33 which delays the reception enable signal (eri) for a period of a reception clock (ckr). In the data transfer unit (13), a signal latched by the first SR-FF circuit (31) is latched a series of two times in time with the reception clock (ckr) to generate the reception permit signal (rro) and a signal latched by the third SR-FF circuit (33) is latched a series of two times in time with the transmission clock (ckw) to generate the transmission permit signal (rwo).

Abstract: The horizontal address and the vertical address of a picture image are arrayed at the lower and upper order sides, respectively, and allocated to a lower order side column address and an upper order side column address of the synchronous DRAM employed as a picture memory, respectively. A bank switching address is allocated between the upper most bit of the horizontal address and the lower most bit of the row address to enable data to be read continuously to achieve high-speed accessing and improve the utilization efficiency of the data bus.

Abstract: In accordance with this invention, in a moving picture decoding apparatus, MB (Macro Block) buffer 111 is provided to thereby absorb difference between read speed from IDCT (Inverse Discrete Cosine Transform) circuit 110 and write speed into reference frame memory 117 of motion compensating section, and DRAM writing buffer 115 is provided to thereby carry out timing adjustment between read and write operations with respect to reference frame memory 117. Namely, adder 114 adds predictive macro block signal S10 from reference frame memory 117 and output signal S9 from MB buffer 111 to write added signal into DRAM writing buffer 115. DRAM writing buffer 115 holds data for a time period until reference frame memory 117 completes preparation for write operation thereafter to write those data into reference frame memory 117. Thus, inexpensive DRAM can be used as reference frame memory.

Abstract: A digital video signal that has been encoded using motion-compensated prediction, transform encoding, and variable-length coding, is decoded using parallel processing. Frames of the video signal are divided into slices made up of a sequence of macroblocks. The signal to be decoded is slice-wise divided for parallel variable-length decoding. Each variable-length-decoded macroblock is divided into its constituent blocks for parallel inverse transform processing. Resulting blocks of difference data are added in parallel to corresponding blocks of reference data. The blocks of reference data corresponding to each macroblock are read out in parallel from reference data memories on the basis of a motion vector associated with the macroblock. Reference data corresponding to each macroblock is distributed for storage among a number of reference data memories.

Abstract: In a video signal transmission system, in which video signals are transformed to high efficiency coded data and are then transmitted, a quantization step size is enlarged when quantizing intra coded picture data to avoid an excessive increase in the amount of data generated. The amount of residual data in a transmission buffer memory is monitored, and frame dropping is initiated when it exceeds a certain predetermined level, but the frame dropping operation is not completed until the amount of residual data falls below a different, smaller predetermined level. Video signals which are sent immediately after a transmission line is connected to a destination are intra coded to enhance system usability.