Abstract: A threshold value calculation device includes: a device state acquirer that acquires a device state of a first device provided in a facility in which a home network is installed during a first period; an occupancy state determiner that determines an occupancy state by people in the facility during the first period based on information acquired from a second device in the facility; a communication log collector that collects a communication log; and a learner that calculates a threshold value for the communication transmitted and received by the first device during a second period that is a period after the first period. The learner calculates the threshold value for each of combinations of one or more states of the first device and one or more states of the people.

Abstract: A detection system includes an obtainer that obtains a first log, the first log being a log of communication in a first network; a determiner that determines whether the first log obtained by the obtainer includes anomaly information indicating anomalous communication in a second network; and a controller that, when the determiner has determined that the first log includes the anomaly information, performs control of notifying of an anomaly in the second network.

Abstract: A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. A sampling phase adjustment circuit (100) adjusts the phase of a sampling clock (CKa). An analog-to-digital converter circuit (104) converts the sensor signal (Ssnc) to a digital sensor signal (Dsnc) in synchronization with the sampling clock (CKsp) phase-adjusted by the sampling phase adjustment circuit. A detection circuit (107) detects the physical quantity based on the digital sensor signal (Dsnc) from the analog-to-digital converter circuit.

Abstract: A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. A phase adjustment circuit (100) receives a reference clock (CKref) and operates in synchronization with an operation clock (CKa), to delay a transition edge of the reference clock by a predetermined number of pulses of the operation clock. A detection circuit (104) detects a physical quantity signal from the sensor signal (Ssnc) using a transition edge of a clock (SSS) from the phase adjustment circuit (100) as the reference.

Abstract: A communication control circuit includes a shift register and a control data selector, and controls controlled units according to a data signal, a clock signal and a strobe signal inputted via three serial signal lines. The shift register serial-to-parallel converts the data signal sequentially taken in according to the clock signal into a converted signal, and outputs the converted signal. The control data selector selects control data for controlling the corresponding controlled unit from the signal from the shift register, in response to a device definition signal for identifying the communication control circuit, and outputs the same control data.

Abstract: A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. A phase adjustment circuit (100) receives a reference clock (CKref) and operates in synchronization with an operation clock (CKa), to delay a transition edge of the reference clock by a predetermined number of pulses of the operation clock. A detection circuit (104) detects a physical quantity signal from the sensor signal (Ssnc) using a transition edge of a clock (SSS) from the phase adjustment circuit (100) as the reference.

Abstract: A physical quantity detection circuit (12) is used for a physical quantity sensor (10) that outputs a sensor signal according to a physical quantity given externally. A sampling phase adjustment circuit (100) adjusts the phase of a sampling clock (CKa). An analog-to-digital converter circuit (104) converts the sensor signal (Ssnc) to a digital sensor signal (Dsnc) in synchronization with the sampling clock (CKsp) phase-adjusted by the sampling phase adjustment circuit. A detection circuit (107) detects the physical quantity based on the digital sensor signal (Dsnc) from the analog-to-digital converter circuit.

Abstract: A video playback device of decoding encoded video data is additionally provided with a compression circuit and a decompression circuit in an existing encoded video decoding circuit. In the compression circuit, a frequency transform circuit transforms played-back video data obtained from the encoded video decoding circuit into frequency coefficient data, which is in turn subjected to IDCT having a reduced order in a frequency compression circuit to obtain compressed video data. The compressed video data, which is image space data having a reduced image size, is stored in a frame memory. The decompression circuit comprises a frequency decompression circuit and an inverse frequency transform circuit which performs a process inverse to that of the compression circuit. The compressed video data from the frame memory is converted by a video output circuit into data which can be displayed, and the resultant data is output to a video display device.