Patents by Inventor Seiichi Nagata
Seiichi Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100294978Abstract: The present invention provides a metal/insulator nanogranular material including: ferromagnetic particles having a composition represented by the formula (1) (Fe1?xCox)100?z(B1?ySiy)z??(1) in which x, y and z each satisfy 0?x?1, 0?y?1, and 0<z?20; and an insulating matrix constituted of an Mg—F compound, the insulating matrix being filled to surround the ferromagnetic particles.Type: ApplicationFiled: May 18, 2010Publication date: November 25, 2010Applicant: DAIDO TOKUSHUKO KABUSHIKI KAISHAInventors: Seiichi NAGATA, Shigenobu KOYAMA, Sanji KANIE
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Publication number: 20080206952Abstract: In a thin film forming step S1, a thin film, having carbon as a main component, is formed on at least one principal surface of a silicon substrate. In a thin film partial removal step S2, of the thin film, a thin film portion at a partial region on the one principal surface is removed. In a porous region forming step S3, the portion of the carbon thin film remaining after the removal of the thin film portion at the partial region in the previous thin film partial removal step S2 is used as a mask and the silicon substrate is anodized in an electrolytic solution containing hydrofluoric acid to selectively form a porous silicon region in a surrounding region including the partial region from which the thin film has been removed. In a remaining thin film portion removal step S4, the remaining portion of the thin film on the one principal surface of the silicon substrate is removed under the oxidizing atmosphere, and at the same time, at least a portion of the porous silicon region is oxidized.Type: ApplicationFiled: September 29, 2005Publication date: August 28, 2008Inventors: Seiichi Nagata, Junichi Murata
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Publication number: 20070275254Abstract: A silicon substrate 1 has a structure in which a depression of a silicon crystal is formed on at least one principal surface 2 side of a crystalline silicon substrate and which has a vitreous region 3 filled in the depression and consisting primarily of silicon oxide. The vitreous region 3 is formed so that the glass transition temperature Tg thereof is lower than that of pure silica glass and not more than 900° C. This configuration realizes the silicon substrate in which internal strain is reduced between glass and the silicon crystal, and a forming method thereof.Type: ApplicationFiled: March 31, 2004Publication date: November 29, 2007Inventor: Seiichi Nagata
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Patent number: 6753589Abstract: A silicon substrate has area-selectively formed porous silicon in which porosity, pore size, and pore size distribution of a porous silicon region and a shape of the porous silicon are controlled. In a silicon forming method of immersing the silicon substrate coated with a mask layer having an opening area into a solution to which forming current is applied, and anodically forming a part of the silicon substrate from the opening area of the mask layer so as to form a porous silicon area in the silicon substrate, the forming current is increased according to degree of growth of the porous silicon such that the interface current density between a growing end part of the porous silicon and silicon substrate in the anodizing process may be substantially kept at constant.Type: GrantFiled: May 17, 2001Date of Patent: June 22, 2004Inventor: Seiichi Nagata
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Patent number: 6601154Abstract: A comparator having a hit signal that is high, before a hit check is established in each way of an address array, and that goes low, when a mishit has been established. When a clock frequency is high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check is established. When the hit check has been established, data read from a way which has the hit is output onto a data line and an operation in the way which has a mishit is stopped.Type: GrantFiled: February 28, 2002Date of Patent: July 29, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita
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Patent number: 6493496Abstract: An optical waveguide has first dielectric substance region which is formed on a surface of the crystalline silicon substrate, and has second dielectric substance region which is formed outside first dielectric substance region. First dielectric substance region is provided with a region in which a concentration of impurity elements for increasing and/or decreasing a refractive index in a direction of transmitting light is periodically increased and decreased, or provided with a corrugated structure, or wherein its width is periodically changed. Therefore, utilizing the property of thermal equilibrium, the optical waveguide has a grating which is thermally stable even at ordinary temperatures.Type: GrantFiled: December 19, 2000Date of Patent: December 10, 2002Inventor: Seiichi Nagata
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Publication number: 20020083267Abstract: A comparator having a hit signal that is high, before a hit check is established in each way of an address array, and that goes low, when a mishit has been established. When a clock frequency is high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check is established. When the hit check has been established, data read from a way which has the hit is output onto a data line and an operation in the way which has a mishit is stopped.Type: ApplicationFiled: February 28, 2002Publication date: June 27, 2002Inventors: Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita
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Patent number: 6389523Abstract: A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.Type: GrantFiled: April 25, 2000Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita
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Publication number: 20010045613Abstract: A silicon substrate has area-selectively formed porous silicon in which porosity, pore size, and pore size distribution of a porous silicon region and a shape of the porous silicon are controlled. In a silicon forming method of immersing the silicon substrate coated with a mask layer having an opening area into a solution to which forming current is applied, and anodically forming a part of the silicon substrate from the opening area of the mask layer so as to form a porous silicon area in the silicon substrate, the forming current is increased according to degree of growth of the porous silicon such that the interface current density between a growing end part of the porous silicon and silicon substrate in the anodizing process may be substantially kept at constant.Type: ApplicationFiled: May 17, 2001Publication date: November 29, 2001Inventor: Seiichi Nagata
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Patent number: 6277662Abstract: This invention concerns a silicon substrate which has area-selectively formed porous silicon, and a forming method thereof, and aims at providing a silicon substrate in which porosity, pore size, and pore size distribution of a porous silicon region and a shape of the porous silicon are controlled, and providing a forming method thereof. In a silicon forming method of immersing the silicon substrate coated with a mask layer having an opening area into a solution to which forming current is applied, and anodically forming a part of the silicon substrate from the opening area of the mask layer so as to form a porous silicon area in the silicon substrate, the forming current is increased according to degree of growth of the porous silicon such that the interface current density between a growing end part of the porous silicon and silicon substrate in the anodizing process may be substantially kept at constant.Type: GrantFiled: June 3, 1999Date of Patent: August 21, 2001Inventor: Seiichi Nagata
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Publication number: 20010002221Abstract: An optical waveguide has first dielectric substance region which is formed on a surface of the crystalline silicon substrate, and has second dielectric substance region which is formed outside first dielectric substance region. First dielectric substance region is provided with a region in which a concentration of impurity elements for increasing and/or decreasing a refractive index in a direction of transmitting light is periodically increased and decreased, or provided with a corrugated structure, or wherein its width is periodically changed. Therefore, utilizing the property of thermal equilibrium, the optical waveguide has a grating which is thermally stable even at ordinary temperatures.Type: ApplicationFiled: December 19, 2000Publication date: May 31, 2001Inventor: Seiichi Nagata
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Patent number: 6222974Abstract: An optical waveguide has first dielectric substance region which is formed on a surface of the crystalline silicon substrate, and has second dielectric substance region which is formed outside first dielectric substance region. First dielectric substance region is provided with a region in which a concentration of impurity elements for increasing and/or decreasing a refractive index in a direction of transmitting light is periodically increased and decreased, or provided with a corrugated structure, or wherein its width is periodically changed. Therefore, utilizing the property of thermal equilibrium, the optical waveguide has a grating which is thermally stable even at ordinary temperatures.Type: GrantFiled: July 28, 1999Date of Patent: April 24, 2001Inventor: Seiichi Nagata
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Patent number: 6070234Abstract: A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.Type: GrantFiled: July 20, 1998Date of Patent: May 30, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita
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Patent number: 5926345Abstract: A contact magnetic head includes a main body and at least three contact pads that contact a magnetic disk, one of which is arranged to send or receive magnetic signals from a disk. A portion of the main body situated between the contact pads has a hardness or deformation characteristic of at least 0.25 mm/kgf, thereby softening that portion of the main body to prevent vibrations of the area of the main body provided with the at least one signal sending/receiving pad.Type: GrantFiled: October 9, 1997Date of Patent: July 20, 1999Assignees: Daido Tokushuko Kabushiki Kaisha, Japan Science and Technology CorporationInventor: Seiichi Nagata
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Patent number: 5860127Abstract: A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.Type: GrantFiled: May 24, 1996Date of Patent: January 12, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita
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Patent number: 5843255Abstract: A connecting pad of a magnetic head element is bonded to a signal conductor of a supporting beam. As a result of the bonding, the magnetic head element is mechanically coupled to the supporting beam and the connecting pad is electrically connected to the signal conductor. Also an auxiliary pad of the magnetic head element is bonded to the signal conductor. This bonding improves the mechanical coupling strength of the magnetic head element to the supporting beam. When the magnetic head element is to be bonded to the supporting beam, one of the pads is bonded to the signal conductor, and thereafter the other pad is bonded to the signal conductor. During the process of the latter bonding, a groove which is previously disposed in the signal conductor blocks heat given for the bonding from being transmitted to the former bonding portion in which bonding has been already completed, thereby preventing the bonding of the former bonding portion from being broken.Type: GrantFiled: February 6, 1996Date of Patent: December 1, 1998Assignees: Daidotokushuko Kabushiki Kaisha, Masaaki MatsuiInventors: Masaaki Matsui, Seiichi Nagata
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Patent number: 5706023Abstract: A method of driving a display device having a matrix of display material elements includes transmitting a picture signal voltage to each picture element electrode during an ON period of a respective switching element, applying a first modulation signal to a first wire during an OFF period of the switching elements associated with the first wire, and applying a second modulation signal to counter electrodes associated with the first wire during the OFF period of the switching elements associated with the first wire. Each picture element electrode of a plurality of the display material elements is connected to the first wire through a respective capacitance.Type: GrantFiled: June 7, 1995Date of Patent: January 6, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Seiichi Nagata, Etsuya Takeda, Tetsuya Kawamura, Yutaka Nanno
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Patent number: 5676304Abstract: A method of bonding a contact-type thin film magnetic head element to a beam for supporting the head element in a contact-type thin film magnetic head during a process of producing the magnetic head is disclosed. A connecting pad of the magnetic head element is made contact with a signal conductor of the supporting beam. Then, a vibration energy of an ultrasonic wave is applied to the contact portion so that the surfaces of the components in the contact portion are caused to diffuse into each other. As a result, a state in which the connecting pad is mechanically coupled and electrically connected to the signal conductor is obtained.Type: GrantFiled: January 30, 1996Date of Patent: October 14, 1997Assignees: Masaaki Matsui, Nipponhatsujyo Kabushikikaisha, Daidotokushuko KabushikikaishaInventors: Masaaki Matsui, Toshiaki Sato, Shinya Ibuka, Seiichi Nagata
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Patent number: 5666133Abstract: Disclosed is a method for driving a liquid crystal display unit, in particular, a method for driving an active matrix type liquid crystal display unit using a thin-film transistor as a switching element. According to the drive method, a plurality of scanning signal power voltages of which levels vary in synchronization with inversion in polarity of an image signal are input to a scanning signal supply circuit, and any of the plural scanning signal power voltages is selected to serve as a scanning signal. Otherwise, some scanning signal power voltages of which levels vary in synchronization with inversion in polarity of the image signal and some scanning signal power voltages of which levels are invariable are input to the scanning signal supply circuit, and any of the plural scanning signal power voltages is selected to serve as a scanning signal.Type: GrantFiled: April 10, 1996Date of Patent: September 9, 1997Assignee: Kyocera CorporationInventors: Shigeki Matsuo, Seiichi Nagata
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Patent number: 5296847Abstract: A method of driving a display unit having matrix-arranged pixel electrodes each connected via a capacitor to a first line, each pixel electrode being connected to a switching element which is electrically connected to an image signal line and scan signal line, and display material held between the pixel electrode and opposing electrode and being AC driven, wherein an image signal voltage is transmitted to the pixel electrode during an on-period of the switching element, and a modulating signal with its voltage reversing alternately for each field is applied to the first line during an off-period of the switching element, thereby changing the potential of the pixel electrode so that the changed potential is superposed upon, or cancelled out from, the image signal voltage, the resultant voltage being applied across the display material.Type: GrantFiled: June 22, 1992Date of Patent: March 22, 1994Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Etsuya Takeda, Yutaka Nanno, Seiichi Nagata