Patents by Inventor Seiichi Orimo
Seiichi Orimo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7144754Abstract: A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.Type: GrantFiled: June 1, 2004Date of Patent: December 5, 2006Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Patent number: 6856017Abstract: A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.Type: GrantFiled: November 17, 1999Date of Patent: February 15, 2005Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Publication number: 20040219719Abstract: A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.Type: ApplicationFiled: June 1, 2004Publication date: November 4, 2004Applicant: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Publication number: 20030006503Abstract: A device includes a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic films.Type: ApplicationFiled: November 17, 1999Publication date: January 9, 2003Inventors: YOSHIYUKI YONEDA, KAZUTO TSUJI, SEIICHI ORIMO, HIDEHARU SAKODA, RYUJI NOMOTO, MASANORI ONODERA, JUNICHI KASAI
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Patent number: 6433418Abstract: A semiconductor device includes a resin package in which a semiconductor chip is sealed, the resin package having a first surface and a second surface opposite to the first surface; a plurality of leads having inner lead parts connected to the semiconductor chip and outer lead parts extending outside the resin package, the outer lead parts being bent along the shape of the resin package so as to form first terminal parts on the second surface and second terminal parts on the first surface; connection means electrically connecting the semiconductor chip and the leads; and a positioning mechanism provided either on the leads or on the resin package, which positions the outer lead parts by engaging a part of the outer lead parts to the resin package. Further, at least one of the leads and/or connection means is cut so as to electrically disconnect the semiconductor chip and the one of the leads and/or connection elements.Type: GrantFiled: April 29, 1999Date of Patent: August 13, 2002Assignee: Fujitsu LimitedInventors: Tetsuya Fujisawa, Mitsutaka Sato, Seiichi Orimo, Kazuhiko Mitobe, Masaaki Seki, Masaki Waki, Toshio Hamano, Katsuhiro Hayashida, Yoshitsugu Katoh, Hiroshi Inoue
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Patent number: 6333564Abstract: A semiconductor device and a method of producing the same, the device including a semiconductor chip; balls which function as external connecting terminals; a substrate which electrically connects the semiconductor chip and the balls; a mold resin which seals at least a part of the semiconductor chip; and a connecting portion sealing resin which seals the connecting portion between the substrate and the semiconductor chip. The semiconductor device is mounted onto a printed circuit board via the balls. The thermal expansion coefficient of the mold resin is matched with the thermal expansion coefficient of the printed circuit board. A side surface holding portion for the holding the side surfaces of the semiconductor chip is formed in the mold resin to restrict thermal deformation of the semiconductor chip.Type: GrantFiled: June 21, 1999Date of Patent: December 25, 2001Assignee: Fujitsu LimitedInventors: Yoshitsugu Katoh, Mitsutaka Sato, Hiroshi Inoue, Seiichi Orimo, Akira Okada, Yoshihiro Kubota, Mitsuo Abe, Toshio Hamano, Yoshitaka Aiba, Tetsuya Fujisawa, Masaaki Seki, Noriaki Shiba
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Publication number: 20010052653Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.Type: ApplicationFiled: July 13, 2001Publication date: December 20, 2001Inventors: Mitsuo Abe, Yoshihiro Kubota, Yoshitsugu Katoh, Michio Hayakawa, Ryuji Nomoto, Mitsutaka Sato, Seiichi Orimo, Hiroshi Inoue, Toshio Hamano
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Patent number: 6288444Abstract: A semiconductor device and a method of producing the semiconductor device are provided. This semiconductor device includes a semiconductor chip, a printed wiring board, a heat spreader, a sealing resin, and solder balls. The printed wiring board is provided with the solder balls on an outer portion and a wiring layer on an inner portion. Wires are bonded to the wiring layer, and an opening is formed in the center of the printed wiring board. The heat spreader is bonded to the printed wiring board, with the semiconductor chip being thermally connected to the stage portion of the heat spreader. The sealing resin is made up of a first sealing resin portion and a second sealing resin portion. The first and second sealing resin portions sandwich the heat spreader.Type: GrantFiled: June 4, 1999Date of Patent: September 11, 2001Assignee: Fujitsu LimitedInventors: Mitsuo Abe, Yoshihiro Kubota, Yoshitsugu Katoh, Michio Hayakawa, Ryuji Nomoto, Mitsutaka Sato, Seiichi Orimo, Hiroshi Inoue, Toshio Hamano
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Patent number: 6255740Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.Type: GrantFiled: May 1, 1997Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Masaki Waki
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Patent number: 6159770Abstract: There is provided a method for fabricating semiconductor devices including resin packages sealing semiconductor elements and external connection terminals respectively resin projections formed on the resin packages and metallic film parts provided to the resin projections. The semiconductor elements are mounted to a lead frame having recess portions located in positions corresponding to positions of the resin projections, metallic film parts being provided in the recess portions. The semiconductor elements are electrically connected to the metallic film parts. The resin packages that seal the semiconductor elements and gate portions are integrally formed with the resin packages. The lead frame is etched so that the resin packages are separated from the lead frame together with the metallic layer parts. The resin packages are attached to an adhesive tape provided to a frame and being used as a carrier.Type: GrantFiled: November 16, 1998Date of Patent: December 12, 2000Assignee: Fujitsu LimitedInventors: Masafumi Tetaka, Shinichiro Maki, Nobuo Ohyama, Seiichi Orimo, Hideharu Sakoda, Yoshiyuki Yoneda, Akihiro Shigeno, Ryoichi Yokoyama, Fumitoshi Fujisaki, Masao Fukunaga, Kazuto Tsuji, Terumi Kamifukumoto, Kenji Itasaka, Masanori Onodera
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Patent number: 6094356Abstract: A semiconductor device including a semiconductor chip, connection parts arranged along one end of the semiconductor chip, and external connection terminals connected to the connection parts.Type: GrantFiled: January 16, 1998Date of Patent: July 25, 2000Assignee: Fujitsu LimitedInventors: Tetsuya Fujisawa, Mitsutaka Sato, Kazuhiko Mitobe, Katsuhiro Hayashida, Masaaki Seki, Seiichi Orimo, Toshio Hamano
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Patent number: 6072239Abstract: A device includes a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic films.Type: GrantFiled: November 6, 1996Date of Patent: June 6, 2000Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Patent number: 6025650Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.Type: GrantFiled: October 30, 1997Date of Patent: February 15, 2000Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Junichi Kasai
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Patent number: 5930603Abstract: A method for producing a semiconductor device includes steps of: a) a positioning board forming process in which concave portions, each of which is located at a position corresponding to a position of a respective projecting electrode of a semiconductor device, and first positioning portions, which are used for determining a position of a sealing resin with respect to the projecting electrode, are integrally formed on a flat-plate member so as to form a positioning board; b) a filling process in which an electrode material for forming the projecting electrode is filled in the concave portions formed on the positioning board; c) a bonding process in which a composite board is formed by mounting a circuit board on the positioning board so as to bond each of the electrode material filled in the concave portions to the circuit board; d) a sealing resin forming process in which a mold having a cavity for forming a sealing resin and second positioning portions for determining a position of the positioning board witType: GrantFiled: May 27, 1997Date of Patent: July 27, 1999Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Seiichi Orimo, Ryuji Nomoto, Masanori Onodera, Hideharu Sakoda
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Patent number: 5656550Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.Type: GrantFiled: March 5, 1996Date of Patent: August 12, 1997Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Masaki Waki