Patents by Inventor Seiichiro Azuma

Seiichiro Azuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5468989
    Abstract: There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: November 21, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Hirotaka Nishizawa, Seiichiro Azuma, Kazuaki Ootoshi, Masataka Miyama, Shuji Kawata, Osamu Kasahara, Sinichi Suzuki
  • Patent number: 5342480
    Abstract: An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: August 30, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Hirotaka Nishizawa, Seiichiro Azuma, Takayuki Yoshitake, Kazuo Tanaka, Mikinori Kawaji, Sinmei Hirano, Toshio Yamada, Yasusi Sekine