Abstract: The characteristic of nonlinear processing with respect to image data is designated by a GUI and the result of the processing quickly displayed. A personal computer 72 displays a GUI image for input on a monitor. When a user designates a nonlinear characteristic on the GUI image by an input device 70, the personal computer 72 extracts a break point approximation function indicating the nonlinear characteristic and displays the same in the GUI image. Further, the personal computer 72 generates a program for executing nonlinear processing indicated by the extracted break point approximation function by a linear array type multiple parallel processor (DSP 80) and downloads the generated program to the DSP 80.

Abstract: According to the SIMD control parallel processing method for performing common operation in parallel in a plurality of elements, comprising first retaining means for retaining operation data specified by n-bit for each of said plurality of elements; second retaining means for previously retaining operated result with all possible combinations comprising said data according to a predetermined operation; and selecting means for selecting said operated data retained in said first retaining means from among said operated results retained by said second retaining means, from among retained data obtained through operation, data corresponding to that resultant from the operation is selected for each element, thereby enabling a configuration to be simplified, smaller and less costly.

Abstract: The present invention relates to an image processing device for converting the number of pixels or scanning lines. In particular, the image processing device according to the present invention comprises an operator for carrying out interpolation operations and a memory for storing filter coefficient sets utilized in the interpolation operations. The memory stores filter coefficient sets each corresponding to each of the phases when the pixel interval of the original image is divided by a prescribed dividing number. Out of these filter coefficient sets, a filter coefficient set that corresponds to the phase closest to that of the pixel data to undergo interpolation operations is then outputted to the operator. The operator then carries out interpolation operations on the pixel data using these filter coefficient sets so that arbitrary format conversion becomes possible.

Abstract: A picture signal processing device for performing picture signal processing such as conversion of the number of pixels or conversion processing for the number of scanning lines. The picture signal processing device includes a plurality of element processors and a controller for performing common control of said element processors. The element processors arrayed in association with pixels arrayed in one-dimensional direction of a digitized two-dimensional picture. The pixels arrayed in one-dimensional direction are chronologically sequentially entered to the element processors.

Abstract: A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.

Abstract: A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and any of outputs of the processor block columns is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

Abstract: A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

Abstract: A digital signal processing apparatus and information processing system provide sufficient arithmetic operation performance to process high rate signals in real time and high programming performance to deal with various applications. A group of processor elements is constituted by individual processor elements each formed by disposing an arithmetic and logic unit on the bit lines of a multiport memory wherein their number is equal to or larger than the number of the data bits in a series of serial data, and the plurality of processor elements constituting the group of processor elements are uniformly controlled by controllers mounted on the same silicon chip. Consequently, the multiport memory functioning as a buffer for input data and the arithmetic and logic unit are closely joined together, so data can be communicated smoothly between them.

Abstract: In a memory device, data stored in memory cells bridging memory cell columns for two lines can be read out in response to an address signal supplied only once. The memory cells (R00-R03), (R10-R13), (R10-R13), (R20-R23)m (R20-R23) and (R30-R33) for the two adjoining lines are connected to common word lines L0, L1, L2. Also, a series of bit lines are sequentially selected by a counter. The data stored in the memory cells bridging the memory cell columns for the two lines can be read out only once by supplying an address signal only one time.

Abstract: A multiport memory having a plurality of serial output ports includes a semiconductor memory for storing data in a plurality of memory elements arrayed in rows and columns and coupled by respective row and column connecting lines. A first register stores data read in parallel from the semiconductor memory via the connecting lines of one of the rows and columns of the arrayed memory elements and serves to supply the data stored therein in serial form to a first one of the serial output ports. The first register is also operative to supply the data stored therein in parallel to a second register for storage therein. The second register is operative to supply the data stored therein to a second one of the serial output ports.

Abstract: A circuit has a multiple port memory and a plurality of processor elements having write and/or read addresses connected to addresses of the multiple port memory. A register, a delay circuit and/or a buffer memory may be formed among the processor elements in dependence on the connections of the write and read addresses.

Abstract: A motion vector detection apparatus comprises; delay circuit for receiving first picture data and for outputting a particular detection range of picture data, block comparison circuit for receiving second picture data with a particular time difference from the first picture data and picture data from the delay circuit and for detecting a difference therebetween for each block of (P.times.Q) picture elements, and determination circuit for determining the matching degree of a picture from the output signal produced by the block comparison circuit, wherein the delay circuit comprises scanning conversion circuit for converting input picture data from conventional horizontal scanning into intra-block scanning and a plurality of shift registers for receiving the first picture data with a delay of one frame, wherein the plurality of shift registers are characterized in that both a first block structuring (P.times.

Abstract: An original picture of an interlace system is magnified or reduced by an integer ration of M to N to form a conversion picture. A unit length U is obtained by dividing the distance between vertically adjacent picture elements of the original or the conversion pictures by N or M, respectively. The positions of the picture elements of both fields of the conversion picture are shifted by .vertline.M-N)/4.vertline..multidot.U from the respective positions that would have been occupied by the picture elements of the conversion picture.

Abstract: A digital filter has an input terminal provided with an input digital signal. A delay circuit connected to the input terminal produces a plurality of delayed digital signals each having a different delay time with respect to the input digital signal. A first circuit adds the input digital signal and/or the plurality of delayed digital signals to one or more digital coefficient signals of the same value so as to produce one or more added digital signals. A circuit multiplies the one or more respective digital coefficient signals by the one or more added digital signals and/or one or more of the plurality of delayed digital signals to produce a plurality of multiplied digital signals.

Abstract: A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product.

Abstract: There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit.

Abstract: A digital signal processing circuit formed on a single integrated chip includes a multiplier for multiplying a multiplicand and multiplier signal to produce a multiple bit product signal having higher order bits delayed more than lower order bits; a first delay circuit for concatenating and delaying the multiplier and multiplicand signals to produce a delayed concatenated signal having higher order bits delayed more than lower order bits; a first selector for selectively supplying either the product signal, the delayed concatenated signal, or a concatenated signal formed from the multiplier and multiplicand signals, as a first selected signal; an adder for adding an input signal to the first selected signal to produce a summed signal; a second delay circuit for delaying a summed signal by a predetermined amount to produce a first delayed summand signal; a third delay circuit for delaying the summand signal to produce a second delayed summand signal having higher order bits delayed more than lower order bits;

Abstract: A digital encoder for use with digital luminance and chrominance signals having black levels includes a level adjusting circuit which adjusts the chrominance and luminance signals to establish a predetermined relationship between the black levels of the level-adjusted chrominance and luminance signals, a chrominance signal with a predetermined relatively large dynamic range thereof modulating circuit which generates a modulated chrominance signal from the level-adjusted chrominance signal, an adding circuit which receives the modulated chrominance signal and the level-adjusted luminance signal and provides an encoded color video signal therefrom, an attenuator circuit which attenuates the encoded color video signal and a circuit for combining sync and burst signals with the attenuated encoded color video signal and with a predetermined pedestal level to provide a composite color video signal within the predetermined dynamic range.

Abstract: An analog to digital converting system for a video signal is disclosed in which an analog video signal is fed to an analog to digital converter, then converted to a digital video signal, a digital burst signal is extracted from the digital video signal thus converted, the digital burst signal is multiplied by first and second AC signals having the same frequency as the burst frequency but different in phase to each other to produce first and second digital product signals, first and second digital signals representing DC components are derived from the first and second digital product signals, and the first and second digital signals are calculated to thereby control the phase of the sampling clock at the analog to digital converter.