Abstract: The movement of a set of element data in a computer is achieved by a plurality of vector registers and a moving unit which can move a set of element data from one vector register to another register in response to one instruction without going through either main memory or the functional units. A selector responds to the instruction to route the output from one register to the input of another and to also provide the appropriate read and write starting addresses.

Abstract: In a processing system including a predetermined number m of vector data processors, a distributor (42) and a selector (47) are used together with a bus (51) in moving vector elements within each vector data processor (16). Connections between a common distributor (39), another distributor (41) and another selector (46) are used in moving vector elements from each vector data processor to at least one other vector data processor (17). Each set of vector registers (21-28), one in each vector data processor, is provided for holding those vector elements of a vector datum which are given element numbers. Preferably, vector elements are moved within each vector data processor when a vector move instruction indicates a start element number which is congruent with zero modulo m. Otherwise, vector elements are moved among the vector data processors with the common distributor controlled in response to the vector move instruction.

Abstract: In a vector processor which is for use in combination with a main memory (11) and includes an input selecting arrangement (36), vector registers (21-28), a vector operation arrangement (31-34), and a store register (38). An output selecting circuit is not used on selecting operand vectors from vectors held in the vector registers. Instead, the vector registers are fixedly coupled to the vector operation arrangement to raise speed of operation and to simplify vector instructions. Preferably, vector memories are provided to retain vectors which need not be held in the vector registers and must have been stored in the main memory. In this event, a vector bypassing arrangement is used to bypass a result vector from the vector operation arrangement to one of the vector memories for storage therein as a bypassed vector. The input selecting arrangement is used on moving the bypassed vector to one of the vector registers.

Abstract: A pair candidate list (73) is formed by selecting minutia pairs with reference to a minutia list (71) showing original position and direction data given for minutiae by principal coordinate systems preliminarily selected on a search and a file fingerprint and those relation data of the minutiae which are substantially independent of the coordinate systems. It is very likely that the pair candidate list shows coarse pairs because the coordinate systems may not yet be optimally matched to each other. One of the coordinate systems is transformed by those optimum amounts to provide transformed position and direction data which are decided by the original position and direction data of the minutia pairs of the pair candidate list. A pair list (86) is formed by precisely selecting minutiae from the pair candidate list with reference to the transformed position and direction data and the original position and direction data given by the other principal coordinate system and to the relation data.