Abstract: A printing system includes: a main printer configured to print an image sheet by sheet; a sub printer communicably connected to the main printer and configured to print an image sheet by sheet; and a storage medium that is configured to store image data of a plurality of images and from which the main printer is able to read out the image data. In response to changing of a state of the sub printer, the sub printer notifies the main printer of a changed state. The main printer regularly checks print situations of the main printer and the sub printer. In accordance with the print situations that are regularly checked, the main printer determines which of the printers is to be used for printing of an image for each of the image data of the plurality of images.

Abstract: According to one embodiment, there is provided an interface circuit including a plurality of units. Each of the plurality of units includes a clock interface, a data interface, and a selector. The clock interface receives a clock and transfers the clock. The data interface receives data and transfers the data. The selector selects a clock and supplies the selected clock to the data interface such that the data interface transfers the data in synchronization with the selected clock.

Abstract: According to one embodiment, a memory controller includes an address conversion table, an address conversion circuit which executes a conversion of a first logical address for accessing to a primary storage device and a conversion of a second logical address for accessing to a secondary storage device, and a control circuit which is configured to access a nonvolatile memory as the primary storage device by receiving the first logical address, and access the nonvolatile memory as the secondary storage device by receiving the second logical address.

Abstract: A multi-processor according to an example of the invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and storing the decoded data in a second memory, an encoding processor element which includes at least one of a plurality of processor elements, encodes the decoded data stored in the second memory in accordance with encoding software stored in a third memory, and stores second compressed data obtained by encoding the decoded data in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.

Abstract: A multi-processor according to an example of the invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and storing the decoded data in a second memory, an encoding processor element which includes at least one of a plurality of processor elements, encodes the decoded data stored in the second memory in accordance with encoding software stored in a third memory, and stores second compressed data obtained by encoding the decoded data in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.

Abstract: A processor system including a plurality of arithmetic units capable of performing arithmetic processing in parallel; a storage which stores data that the arithmetic units use for arithmetic processing; a plurality of DMA controllers which perform data transfer between the arithmetic units, and between the arithmetic units and the storage in parallel with processing of a host processor; and a DMA control circuit which controls start-up the arithmetic units and the DMA controllers in parallel with processing of the host processor.

Abstract: A multi-processor according to an example of the invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and storing the decoded data in a second memory, an encoding processor element which includes at least one of a plurality of processor elements, encodes the decoded data stored in the second memory in accordance with encoding software stored in a third memory, and stores second compressed data obtained by encoding the decoded data in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.

Abstract: Embodiments of the systems and methods presented herein may provide memory security in a semiconductor device or a computing system using an address encryption section operable to encrypt a write address or a read address, a data encrypting section operable to encrypt data to be written, a write section operable to write encrypted data at an encrypted write address corresponding to a memory, a read section operable to read encrypted data from the encrypted read address corresponding to the memory and a data decryption section operable to decrypt the read encrypted data to obtain read data corresponding to the read address.

Abstract: A processor system, comprising: a plurality of arithmetic units capable of performing arithmetic processings in parallel; a storage which stores data that said plurality of arithmetic units use for arithmetic processings; a plurality of DMA controllers which perform data transfer between said plurality of arithmetic units, and between said plurality of arithmetic units and said storage in parallel with processings of a host processor; and a DMA control circuit which controls start-up of said plurality of arithmetic units and said plurality of DMA controllers in parallel with processings of said host processor.

Abstract: An image processing system comprises: a plurality of operation pipelines to operate an inputted image data; a switching channel to switch a data transfer path to input operation results, which are outputted from the plurality of operation pipelines, to the plurality of operation pipeline again; and a control circuit to control switching of the data transfer path by the switching channel and to control an operation in the plurality of operation pipelines, the control circuit carrying out a scheduling of a plurality of operations, which form (n−k+1) unit operations from a unit operation k (1<k<n) to a unit operation n (n is a positive integer) of unit operations 1 to n, the plurality of operations prevented from overlapping with each other at the same predetermined operation time in the same operation pipeline when a unit operation included in the plurality of operations is executed by the plurality of operation pipelines.

Abstract: A system for providing an information space onto a network has a user mediation section for exchanging information with users, and a supply mediation section for exchanging information with information supply sections. The system has a basic data management section for storing basic data which includes a table that indicates correspondence between the information supply sections and key symbols, and a plurality of materials used to form an information space. The system also has a space management section including a space producer and space manager. The space producer forms an information space corresponding to a key symbol in response to a key symbol that represents a search target of each user. The space manager provides each information space to the corresponding user while placing a character that represents actions of the corresponding user in the information space.

Abstract: An image processing system comprises: a plurality of operation pipelines to operate an inputted image data; a switching channel to switch a data transfer path to input operation results, which are outputted from the plurality of operation pipelines, to the plurality of operation pipeline again; and a control circuit to control switching of the data transfer path by the switching channel and to control an operation in the plurality of operation pipelines, the control circuit carrying out a scheduling of a plurality of operations, which form (n−k+1) unit operations from a unit operation k (1<k<n) to a unit operation n (n is a positive integer) of unit operations 1 to n, the plurality of operations prevented from overlapping with each other at the same predetermined operation time in the same operation pipeline when a unit operation included in the plurality of operations is executed by the plurality of operation pipelines.