Patents by Inventor Seiji Hinata

Seiji Hinata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6378083
    Abstract: A watch dog timer capable of detecting a runaway state of a system including a CPU and DMAC has a watch dog timer and a count clock controller. The watch dog timer counts the number of clock and stores a count result, and transmits a watch dog time out signal to other devices in the system if the number of clocks is over a predetermined value. The count clock controller receives the clock and transmits the clock to the watch dog timer, and halts the transmission of the clock to the watch dog timer when the CPU transmits a bus permission signal to the DMAC.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: April 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Yamanaka, Seiji Hinata
  • Patent number: 5677859
    Abstract: An arithmetic operation processing unit provided with an external program memory storing a high speed instruction group for executing a specific routine of arithmetic operations which require high speed execution is shown. The arithmetic operation processing unit comprises a start address register for holding a starting address of the specific routine of arithmetic operations and an end address register for holding an end address of the specific routine of arithmetic operations, an FIFO type RAM for storing microcodes obtained by decoding the high speed instruction group. The high speed instruction group stored in the program memory is sequentially read out by a first instruction execution control means from the start address to the end address and decoded into corresponding microcodes when a high speed instruction group decoding instruction is executed. The microcodes thus obtained are then stored in the FIFO type RAM.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: October 14, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Kanayama, Seiji Hinata, Toshiyuki Shinoda, Tadashi Yabuta
  • Patent number: 5634106
    Abstract: A micro-computer system using a DRAM can refresh the DRAM in a certain interval cycle to maintain the memory contents or refresh the DRAM memory even when the system is set into the standby mode and the clock generator has stopped providing clock timing signals to the memory refreshing circuit. Accordingly, the DRAM memory is refreshed by automatically changing from the interval refresh mode to the self refresh mode when the system operation changes from the normal operation to the standby operation, thus achieving low system power consumption.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: May 27, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsumi Yaezawa, Seiji Hinata