Patents by Inventor Seiji Kajiwara
Seiji Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240099014Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Shunsuke TAKUMA, Yuji TOTOKI, Seiji SHIMABUKURO, Tatsuya HINOUE, Kengo KAJIWARA, Akihiro TOBIOKA
-
Patent number: 8822321Abstract: According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformally formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns.Type: GrantFiled: August 29, 2013Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Seiji Kajiwara
-
Publication number: 20140004691Abstract: According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformally formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: KABUSHIKI KAISHA TOSHIHAInventor: Seiji KAJIWARA
-
Patent number: 8551875Abstract: According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformably formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns.Type: GrantFiled: February 2, 2012Date of Patent: October 8, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Seiji Kajiwara
-
Publication number: 20120289039Abstract: According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformally formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns.Type: ApplicationFiled: February 2, 2012Publication date: November 15, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Seiji KAJIWARA
-
Patent number: 8309469Abstract: A method of fabricating a semiconductor device includes forming core material patterns comprising first films separated from another above a substrate; modifying surfaces of core material patterns so a second film is formed, selectively etchable, with first films internally remaining, the second film not covering a base layer of core material patterns between core material patterns; covering an upper surface and sides of the second film and forming a third film on the substrate; etching back the third film to expose an upper surface of the second film and the base layer of core material patterns between the patterns, causing the third film to selectively remain; removing the second film more rapidly than the first and third films; and patterning the base layer with the first and third films remaining on the base layer serving as a mask after the second film has been removed, forming a base layer pattern.Type: GrantFiled: February 17, 2009Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Seiji Kajiwara
-
Publication number: 20090298274Abstract: A method of fabricating a semiconductor device includes forming core material patterns comprising first films separated from each other above a substrate, modifying surfaces of the core material patterns so that a second film is formed so as to be selectively etchable with the first films internally remaining, covering an upper surface and sides of the second film and forming a third film on the substrate, etching back the third film so that an upper surface of the second film is exposed and a base layer of the core material patterns is exposed between the patterns, and causing the third film to selectively remain, removing the second film more rapidly than the first and third films, and patterning the base layer with the first and third films remaining on the base layer serving as a mask after the second film has been removed, thereby forming a base layer pattern.Type: ApplicationFiled: February 17, 2009Publication date: December 3, 2009Inventor: Seiji Kajiwara
-
Publication number: 20090179004Abstract: A pattern formation method according to one embodiment includes: depositing a first C-containing film and a first inorganic layer pattern above a workpiece, the first inorganic layer pattern being comprised of linear patterns arranged in parallel and having a longitudinal direction in a predetermined direction; depositing a second C-containing film and a second inorganic layer pattern above the first C-containing film and the first inorganic layer pattern, at least a portion of the second inorganic layer pattern being comprised of linear patterns arranged in parallel and intersecting with the first inorganic layer pattern; removing the first and second C-containing films other than regions located substantially directly below at least one of the first and second inorganic layer patterns by etching, to form an etching mask including the first and second inorganic layer patterns and the etched first and second C-containing films; and forming a pattern of the workpiece by etching the workpiece using the etchingType: ApplicationFiled: January 8, 2009Publication date: July 16, 2009Inventor: Seiji KAJIWARA
-
Publication number: 20010005634Abstract: A dry etching method using an etching gas in RIE wherein the etching gas contains CH2F2 at a ratio of 20% or more based on the entire volume of the etching gas. Where another carbon-containing gas is employed as an etching gas, a mixed gas containing this carbon-containing gas and CH2F2 is included in the etching gas at a ratio of 20% or more, and the content of CH2F2 is set to 5% or more.Type: ApplicationFiled: December 27, 2000Publication date: June 28, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Seiji Kajiwara
-
Patent number: 4637489Abstract: An electroacoustic transducer has a front air chamber in front of the diaphragm that vibrates upon receiving sound waves or produces sound waves upon vibration and a back air chamber provided in the rear of the diaphragm. The electroacoustic transducer of the present invention further includes an auxiliary air chamber that is provided in the rear of the back air chamber that is coupled thereto by through holes. The auxiliary air chamber is divided into at least two smaller air chambers which are coupled to each other by a small orifice.Type: GrantFiled: September 4, 1985Date of Patent: January 20, 1987Assignees: Nippon Chem-Con Corp., Hideo KoideInventors: Masaya Iwanaka, Seiji Kajiwara
-
Patent number: 4417153Abstract: A single-ended switching circuit is constituted by a primary winding of a transformer, a switching circuit connected between the primary winding and a DC power supply and on-off operated with a predetermined cycle and also with a predetermined "on" period and a resonance capacitor connected in parallel with the primary winding. A magnetic amplifier, a rectifying element and a choke coil are connected in series between a secondary side circuit of the transformer and the load. The magnetic amplifier includes a saturable reactor which is held saturated during a half cycle of the voltage induced in a secondary winding of the transformer and remains unsaturated during the other half cycle of the voltage.Type: GrantFiled: February 16, 1982Date of Patent: November 22, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Toshihiro Onodera, Youichi Masuda, Akira Nakajima, Yoshio Takamura, Seiji Kajiwara, Shoichi Higo
-
Patent number: 4401902Abstract: A switching element is connected between a power supply and the primary winding of a transformer, and it is on-off controlled with a predetermined cycle and with a predetermined conducting period. The secondary winding of the transformer is connected to a parallel circuit of a filtering capacitor and a load via a rectifier diode and a choke coil. A closed circuit, to which the reflux current of the choke coil flows through the parallel circuit of the filtering capacitor and load, is formed by a reflux diode.Type: GrantFiled: February 16, 1982Date of Patent: August 30, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Toshihiro Onodera, Youichi Masuda, Akira Nakajima, Yoshio Takamura, Seiji Kajiwara, Shoichi Higo
-
Patent number: 4399376Abstract: A switching element, a transformer having a primary winding connected through said switching element to a DC power supply and a resonance capacitor connected in parallel with the primary winding of said transformer constitute a single-ended switching circuit. A magnetic amplifier is connected between the secondary side circuit of the transformer of the single-ended switching circuit and a rectifying/smoothing circuit, thus forming a high frequency switching circuit.Type: GrantFiled: February 16, 1982Date of Patent: August 16, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Toshihiro Onodera, Koichiro Inomata, Michio Hasegawa, Yoshio Takamura, Seiji Kajiwara, Shoichi Higo