Patents by Inventor Seiji Matsuura

Seiji Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916285
    Abstract: A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 ?/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 ?m when viewed at a viewing angle of 120°.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 27, 2024
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Koichi Suzuki, Seiji Take, Daisuke Matsuura
  • Patent number: 10281821
    Abstract: An exposure apparatus includes a polarizing member polarizing illumination light, and a filter having at least one opening. The polarizing member includes a first polarizing unit and a second polarizing unit arranged so as to surround the first polarizing unit. The second polarizing unit is configured so as to polarize the illumination light entering the second polarizing unit in the circumferential direction along the outer circumference of the first polarizing unit. At least a portion of the first polarizing unit is configured to polarize the illumination light in the direction orthogonal to the polarization direction in a part of the second polarizing unit located on the side opposite to the central part of the first polarizing unit. The openings are arranged in the filter so that the illumination light at the post stage of the filter and the polarizing member includes the illumination light polarized by the first and second polarizing units.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Seiji Matsuura
  • Publication number: 20180217505
    Abstract: To shorten a time required for a risk degree determination in a lithography compliance check. When each detection point extracted in a lithography compliance check is categorized, a vertically long detection area and a horizontally long detection area both centering on the detection point are provided for each detection point. Further, a plurality of detection points are categorized based on the identity of each pattern included in the vertically long detection area and the identity of each pattern included in the horizontally long detection area.
    Type: Application
    Filed: November 30, 2017
    Publication date: August 2, 2018
    Applicant: Renesas Electronics Corporation
    Inventor: Seiji MATSUURA
  • Publication number: 20180081275
    Abstract: An exposure apparatus includes a polarizing member polarizing illumination light, and a filter having at least one opening. The polarizing member includes a first polarizing unit and a second polarizing unit arranged so as to surround the first polarizing unit. The second polarizing unit is configured so as to polarize the illumination light entering the second polarizing unit in the circumferential direction along the outer circumference of the first polarizing unit. At least a portion of the first polarizing unit is configured to polarize the illumination light in the direction orthogonal to the polarization direction in a part of the second polarizing unit located on the side opposite to the central part of the first polarizing unit. The openings are arranged in the filter so that the illumination light at the post stage of the filter and the polarizing member includes the illumination light polarized by the first and second polarizing units.
    Type: Application
    Filed: July 1, 2017
    Publication date: March 22, 2018
    Inventor: Seiji MATSUURA
  • Publication number: 20100296069
    Abstract: There is provided a pattern division method to form crowded patterns accurately on a substrate includes acquiring a mask pattern, dividing a predetermine area into a plurality of areas to prepare a division pattern in which the plurality of the areas are classified into first and second groups, generating a reduced mask pattern by reducing each of two or more patterns laid out in the object mask pattern substantially toward the center of the particular pattern, overlapping the division pattern with the reduced mask pattern and extracting the reduced patterns overlapped with the area classified as the first group of the division pattern to generate a first reduced mask pattern, and restoring the reduced patterns laid out in the first reduced mask pattern to the original size before generation of the reduced mask pattern.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 25, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Seiji Matsuura
  • Patent number: 7572558
    Abstract: A photomask is to be used for exposure of a semiconductor wafer with the dipole illumination light, and includes a main opening, a first assist opening, a second assist opening, a third assist opening and a fourth assist opening. Each of the assist openings is located so that the central point thereof is deviated from both of a first straight line parallel to a first direction and passing the central point of the main opening, and a second straight line parallel to a second direction and passing the central point of the main opening. Here, the first direction is the direction among in-plane directions of the photomask that is parallel to an alignment direction of an effective light source distribution of the dipole illumination light. Also, the second direction is the direction among in-plane directions of the photomask that is perpendicular to the alignment direction.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: August 11, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Matsuura
  • Patent number: 7537864
    Abstract: A method of designing hole patterns for arranging hole patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing, wherein a grid is provided on the pattern drawing with a space smaller than a minimum pitch allowed by the design rule of the semiconductor integrated circuit, and the hole patterns are provided at lattice points, which are the intersections of the grid. Flexibility of hole pattern arrangement is improved and the quality of hole pattern arrangement can be easily evaluated.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: May 26, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Masashi Fujimoto, Seiji Matsuura
  • Patent number: 7295286
    Abstract: The exposure device includes a polarizing plate and an illumination diaphragm. The polarizing plate is located in an optical path between a light source and a photomask, serving as a polarizing unit that polarizes an illuminating light from the light source in the first and the second direction orthogonal to the optical axis. The illumination diaphragm is a so-called quadruple illumination diaphragm, which includes four openings. The first opening and the second opening are located on a straight line running parallel to a third direction perpendicular to the optical axis and passing the center point of the illumination diaphragm, across the center point from each other. Likewise, the third opening and the fourth opening are located on a straight line running parallel to a fourth direction perpendicular to the optical axis and passing the center point, across the center point from each other.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: November 13, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Matsuura
  • Publication number: 20070212617
    Abstract: A photomask is to be used for exposure of a semiconductor wafer with the dipole illumination light, and includes a main opening, a first assist opening, a second assist opening, a third assist opening and a fourth assist opening. Each of the assist openings is located so that the central point thereof is deviated from both of a first straight line parallel to a first direction and passing the central point of the main opening, and a second straight line parallel to a second direction and passing the central point of the main opening. Here, the first direction is the direction among in-plane directions of the photomask that is parallel to an alignment direction of an effective light source distribution of the dipole illumination light. Also, the second direction is the direction among in-plane directions of the photomask that is perpendicular to the alignment direction.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Seiji Matsuura
  • Publication number: 20070002302
    Abstract: The exposure device includes a polarizing plate and an illumination diaphragm. The polarizing plate is located in an optical path between a light source and a photomask, serving as a polarizing unit that polarizes an illuminating light from the light source in the first and the second direction orthogonal to the optical axis. The illumination diaphragm is a so-called quadruple illumination diaphragm, which includes four openings. The first opening and the second opening are located on a straight line running parallel to a third direction perpendicular to the optical axis and passing the center point of the illumination diaphragm, across the center point from each other. Likewise, the third opening and the fourth opening are located on a straight line running parallel to a fourth direction perpendicular to the optical axis and passing the center point, across the center point from each other.
    Type: Application
    Filed: May 24, 2006
    Publication date: January 4, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Seiji Matsuura
  • Publication number: 20050142454
    Abstract: A method of designing hole patterns for arranging hole patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing, wherein a grid is provided on the pattern drawing with a space smaller than a minimum pitch allowed by the design rule of the semiconductor integrated circuit, and the hole patterns are provided at lattice points, which are the intersections of the grid. Flexibility of hole pattern arrangement is improved and the quality of hole pattern arrangement can be easily evaluated.
    Type: Application
    Filed: December 27, 2004
    Publication date: June 30, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Masashi Fujimoto, Seiji Matsuura
  • Publication number: 20030087535
    Abstract: In a lithography process in the fabrication of a semiconductor device, a resist liquid is sprayed onto a substrate having vias with an aspect ratio of at least 1 while spinning the substrate at a constant speed of rotation. The substrate is then rotated for a prescribed time at a speed of rotation that is less than the speed of rotation during spraying, whereby the fill factor in vias and the state of coating at via edges are adjusted. After undergoing this step, the substrate is rotated at a speed of rotation that is greater than the speed of rotation during spraying to determine the film thickness.
    Type: Application
    Filed: November 1, 2002
    Publication date: May 8, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Seiji Matsuura
  • Publication number: 20020075458
    Abstract: A method for correcting a spherical aberration of a projection lens in an exposure system includes the step of measuring a best focus shift amount by using an exposure light passed by a half-tone phase shift mask having a specific configuration, and correcting the spherical aberration of the projection lens based on the best focus shift amount measured.
    Type: Application
    Filed: December 13, 2001
    Publication date: June 20, 2002
    Applicant: NEC CORPORATION
    Inventor: Seiji Matsuura
  • Patent number: 6335125
    Abstract: A photomask has an isolated residual pattern formed on it, and a translucent film formed on both sides of this isolated residual pattern, with a space pattern part therebetween, the width of the translucent film being approximately equal to the line width of the isolated residual pattern.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: January 1, 2002
    Assignee: NEC Corporation
    Inventor: Seiji Matsuura
  • Publication number: 20010038951
    Abstract: A photomask has an isolated residual pattern formed on it, and a translucent film formed on both sides of this isolated residual pattern, with a space pattern part therebetween, the width of the translucent film being approximately equal to the line width of the isolated residual pattern.
    Type: Application
    Filed: March 19, 1999
    Publication date: November 8, 2001
    Applicant: Seiji Matsuura
    Inventor: SEIJI MATSUURA
  • Patent number: 6310684
    Abstract: There is provided a method of measuring spherical aberration in a projection system in which a mask pattern is projected in a reduced scale with a light having a wavelength of &lgr;, including the steps of (a) projecting a first mask pattern onto a photosensitive object in a reduced scale, the first mask pattern being defined by light-permeable portions and light-impermeable portions each sandwiched between the light-permeable portions, each of the light-permeable portions having a width equal to the wavelength &lgr;, (b) projecting a second mask pattern onto the photosensitive object in a reduced scale, the second mask pattern being defined by light-permeable portions and light-impermeable portions each sandwiched between the light-permeable portions.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: October 30, 2001
    Assignee: NEC Corporation
    Inventor: Seiji Matsuura
  • Publication number: 20010028457
    Abstract: In a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer, the first alignment marks and second alignment marks are disposed so as to be approximately as close to each other as a diffraction grating distance X.
    Type: Application
    Filed: June 8, 2001
    Publication date: October 11, 2001
    Applicant: NEC CORPORATION
    Inventor: Seiji Matsuura
  • Patent number: 6271919
    Abstract: In a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer, the first alignment marks and second alignment marks are disposed so as to be approximately as close to each other as a diffraction grating distance X.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: August 7, 2001
    Assignee: NEC Corporation
    Inventor: Seiji Matsuura
  • Publication number: 20010002559
    Abstract: A method for producing cutting tools incorporated in the present invention is carried out as follows: a shank portion and a drill portion are formed separately such that the inner diameter of a hole made in the shank portion is slightly smaller than the outer diameter of the drill portion. The rear of the drill portion is forcibly inserted into the hole of the shank portion at normal temperature which is room temperature. The diameter of the inner wall of the hole is thereby enlarged, resulting in a tight fitting. After the insertion of the drill portion in the shank portion, the drill portion may be ground to form a drill edge. Before the insertion of the drill portion in the shank portion, the shank portion may be quenched under vacuum or the like, or the surface of the shank portion may be hardened by nitriding.
    Type: Application
    Filed: January 31, 2001
    Publication date: June 7, 2001
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Yasuyoshi Fujii, Seiji Matsuura, Kazuhiro Kaneko
  • Patent number: 6208469
    Abstract: This invention is a method of adjusting a reduction projection exposure device having a light source, an illumination optical system, and a reduction image-forming optical system.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: March 27, 2001
    Assignee: NEC Corporation
    Inventor: Seiji Matsuura