Patents by Inventor Seiji Narui
Seiji Narui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7418685Abstract: Bit lines and a pair of two tungsten wires having the same widths are formed at a portion where a through-hole is to be formed such that the bit lines and the tungsten wires are arranged at regular intervals. A through-hole for connection to another wiring layer is formed between the tungsten wires. A connection wiring made of tungsten is formed over the through-hole so as to have a predetermined margin around the through-hole. In a photolithography process, a slit having a small width enough to be insensitive to a photo-resist is formed so as to span the through-hole.Type: GrantFiled: June 25, 2004Date of Patent: August 26, 2008Assignees: Elpida Memory, Inc., Hitachi Ulsi Systems, Co., Ltd., Hitachi Ltd.Inventors: Yuko Watanabe, Koji Arai, Seiji Narui
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Publication number: 20080012107Abstract: Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.Type: ApplicationFiled: July 3, 2007Publication date: January 17, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Satoshi Isa, Mitsuaki Katagiri, Kyoichi Nagata, Seiji Narui
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Publication number: 20080008013Abstract: A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.Type: ApplicationFiled: June 15, 2007Publication date: January 10, 2008Inventors: Takeshi OHGAMI, Seiji Narui
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Publication number: 20060081972Abstract: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.Type: ApplicationFiled: October 12, 2005Publication date: April 20, 2006Inventors: Mitsuaki Katagiri, Hiroya Shimizu, Fumiyuki Osanai, Yasushi Takahashi, Seiji Narui
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Patent number: 6954386Abstract: A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.Type: GrantFiled: February 20, 2003Date of Patent: October 11, 2005Assignees: Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.Inventors: Seiji Narui, Kenji Mae, Makoto Morino, Shuichi Kubouchi
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Patent number: 6924525Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 ?/? or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: GrantFiled: August 19, 2003Date of Patent: August 2, 2005Assignee: Hitachi, Ltd.Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Publication number: 20050028125Abstract: Bit lines and a pair of two tungsten wires having the same widths are formed at a portion where a through-hole is to be formed such that the bit lines and the tungsten wires are arranged at regular intervals. A through-hole for connection to another wiring layer is formed between the tungsten wires. A connection wiring made of tungsten is formed over the through-hole so as to have a predetermined margin around the through-hole. In a photolithography process, a slit having a small width enough to be insensitive to a photo-resist is formed so as to span the through-hole.Type: ApplicationFiled: June 25, 2004Publication date: February 3, 2005Inventors: Yuko Watanabe, Koji Arai, Seiji Narui
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Publication number: 20040031980Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: ApplicationFiled: August 19, 2003Publication date: February 19, 2004Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Publication number: 20030202390Abstract: A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.Type: ApplicationFiled: February 20, 2003Publication date: October 30, 2003Inventors: Seiji Narui, Kenji Mae, Makoto Morino, Shuichi Kubouchi
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Patent number: 6635918Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: GrantFiled: November 17, 2000Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Patent number: 6563750Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: April 30, 2002Date of Patent: May 13, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Publication number: 20020118587Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: ApplicationFiled: April 30, 2002Publication date: August 29, 2002Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Patent number: 6411543Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: GrantFiled: January 8, 2001Date of Patent: June 25, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
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Patent number: 6388941Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: July 13, 2001Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi, ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Patent number: 6372554Abstract: A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or “synthetic” pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.Type: GrantFiled: September 7, 1999Date of Patent: April 16, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Keizo Kawakita, Kazuhiko Kajigaya, Seiji Narui, Kiyoshi Nakai, Kazunari Suzuki, Hideaki Tsugane, Fumiyoshi Sato
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Publication number: 20020006062Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: ApplicationFiled: July 13, 2001Publication date: January 17, 2002Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda
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Publication number: 20010001598Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: ApplicationFiled: January 8, 2001Publication date: May 24, 2001Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
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Patent number: 6201728Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: GrantFiled: February 8, 1999Date of Patent: March 13, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
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Patent number: 6150689Abstract: The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.Type: GrantFiled: January 13, 1997Date of Patent: November 21, 2000Assignee: Hitachi, Ltd.Inventors: Seiji Narui, Tetsu Udagawa, Kazuhiko Kajigaya, Makoto Yoshida
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Patent number: 5905685Abstract: In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.Type: GrantFiled: October 15, 1997Date of Patent: May 18, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Masayuki Nakamura, Masatoshi Hasegawa, Seiji Narui, Yousuke Tanaka, Shinichi Miyatake, Shuichi Kubouchi, Kazuhiko Kajigaya