Patents by Inventor Seiji Nonoguchi
Seiji Nonoguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11522132Abstract: A storage device includes a first electrode, a second electrode, and a storage layer. The second electrode is disposed to oppose the first electrode. The storage layer is provided between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), transition metal, and oxygen. The storage layer has a non-linear resistance characteristic, and the storage layer is caused to be in a low-resistance state by setting an application voltage to be equal to or higher than a predetermined threshold voltage and is caused to be in a high-resistance state by setting the application voltage to be lower than the predetermined threshold voltage to thereby have a rectification characteristic.Type: GrantFiled: December 6, 2018Date of Patent: December 6, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuhiro Ohba, Seiji Nonoguchi, Hiroaki Sei, Takeyuki Sone, Minoru Ikarashi
-
Patent number: 11211123Abstract: A disclosed semiconductor device includes a memory cell with a first terminal, a second terminal, a memory element having a first resistance state and a second resistance state, and a nonlinear element, and a drive controller that performs a first operation that allows the memory element to be in the first resistance state, a second operation that allows the memory element to be in the second resistance state, a third operation in which the voltage of the first and second terminals is caused to be different from each other and a value of electric current flowing between the first terminal and the second terminal is caused to be limited to a first current value to determine the resistance state, and a fourth operation in which the current value is caused to be limited to a second current value. The drive controller performs the fourth operation after at least one of the first to third operations.Type: GrantFiled: November 30, 2018Date of Patent: December 28, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Takeyuki Sone, Seiji Nonoguchi, Jun Okuno, Hiroyuki Fujita
-
Patent number: 11183633Abstract: A switch device includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).Type: GrantFiled: September 12, 2017Date of Patent: November 23, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroaki Sei, Kazuhiro Ohba, Takeyuki Sone, Seiji Nonoguchi, Minoru Ikarashi
-
Patent number: 11152428Abstract: There is provided a selection device that includes a first electrode, a second electrode opposed to the first electrode, a semiconductor layer provided between the first electrode and the second electrode, and including at least one kind of chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one kind of first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si), and a first heat bypass layer provided at least in a portion around the semiconductor layer between the first electrode and the second electrode and having higher thermal conductivity than the semiconductor layer.Type: GrantFiled: April 6, 2018Date of Patent: October 19, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Minoru Ikarashi, Takeyuki Sone, Seiji Nonoguchi, Hiroaki Sei, Kazuhiro Ohba
-
Publication number: 20210183443Abstract: A disclosed semiconductor device includes a memory cell with a first terminal, a second terminal, a memory element having a first resistance state and a second resistance state, and a nonlinear element, and a drive controller that performs a first operation that allows the memory element to be in the first resistance state, a second operation that allows the memory element to be in the second resistance state, a third operation in which the of of the first and second terminals is caused to be different from each other and a value of electric current flowing between the first terminal and the second terminal is caused to be limited to a first current value to determine the resistance state, and a fourth operation in which the current value is caused to be limited to a second current value. The drive controller performs the fourth operation after at least one of the first to third operations.Type: ApplicationFiled: November 30, 2018Publication date: June 17, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takeyuki SONE, Seiji NONOGUCHI, Jun OKUNO, Hiroyuki FUJITA
-
Patent number: 11018189Abstract: A storage apparatus includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.Type: GrantFiled: March 15, 2018Date of Patent: May 25, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Seiji Nonoguchi, Katsuhisa Aratani, Kazuhiro Ohba
-
Patent number: 11004902Abstract: Provided is a circuit element that includes paired inert electrodes, and a switch layer provided between the paired inert electrodes, that functions as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.Type: GrantFiled: April 24, 2017Date of Patent: May 11, 2021Assignee: SONY CORPORATIONInventors: Minoru Ikarashi, Seiji Nonoguchi, Takeyuki Sone, Hiroaki Sei, Kazuhiro Ohba, Jun Okuno
-
Patent number: 10879312Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.Type: GrantFiled: August 8, 2019Date of Patent: December 29, 2020Assignee: SONY CORPORATIONInventors: Hiroaki Sei, Kazuhiro Ohba, Seiji Nonoguchi
-
Publication number: 20200350498Abstract: A storage device includes a first electrode, a second electrode, and a storage layer. The second electrode is disposed to oppose the first electrode. The storage layer is provided between the first electrode and the second electrode, and includes one or more chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), transition metal, and oxygen. The storage layer has a non-linear resistance characteristic, and the storage layer is caused to be in a low-resistance state by setting an application voltage to be equal to or higher than a predetermined threshold voltage and is caused to be in a high-resistance state by setting the application voltage to be lower than the predetermined threshold voltage to thereby have a rectification characteristic.Type: ApplicationFiled: December 6, 2018Publication date: November 5, 2020Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuhiro OHBA, Seiji NONOGUCHI, Hiroaki SEI, Takeyuki SONE, Minoru IKARASHI
-
Patent number: 10804321Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.Type: GrantFiled: August 7, 2019Date of Patent: October 13, 2020Assignee: Sony Semiconductor Solutions CorporationInventors: Kazuhiro Ohba, Hiroaki Sei, Seiji Nonoguchi, Takeyuki Sone, Minoru Ikarashi
-
Publication number: 20200052036Abstract: A selection device according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; a semiconductor layer provided between the first electrode and the second electrode, and including at least one kind of chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S), and at least one kind of first element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), carbon (C), germanium (Ge), and silicon (Si); and a first heat bypass layer provided at least in a portion around the semiconductor layer between the first electrode and the second electrode and having higher thermal conductivity than the semiconductor layer.Type: ApplicationFiled: April 6, 2018Publication date: February 13, 2020Inventors: MINORU IKARASHI, TAKEYUKI SONE, SEIJI NONOGUCHI, HIROAKI SEI, KAZUHIRO OHBA
-
Publication number: 20200052040Abstract: A storage apparatus according to an embodiment of the present disclosure includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.Type: ApplicationFiled: March 15, 2018Publication date: February 13, 2020Inventors: SEIJI NONOGUCHI, KATSUHISA ARATANI, KAZUHIRO OHBA
-
Publication number: 20190371859Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.Type: ApplicationFiled: August 8, 2019Publication date: December 5, 2019Inventors: HIROAKI SEI, KAZUHIRO OHBA, SEIJI NONOGUCHI
-
Publication number: 20190363134Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuhiro OHBA, Hiroaki SEI, Seiji NONOGUCHI, Takeyuki SONE, Minoru IKARASHI
-
Publication number: 20190296083Abstract: [Object] To provide a circuit element, a storage device, electronic equipment, a method of writing information into a circuit element, and a method of reading information from a circuit element. [Solution] The circuit element includes: paired inert electrodes; and a switch layer provided between the paired inert electrodes, configured to function as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.Type: ApplicationFiled: April 24, 2017Publication date: September 26, 2019Inventors: MINORU IKARASHI, SEIJI NONOGUCHI, TAKEYUKI SONE, HIROAKI SEI, KAZUHIRO OHBA, JUN OKUNO
-
Patent number: 10418416Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.Type: GrantFiled: December 10, 2013Date of Patent: September 17, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroaki Sei, Kazuhiro Ohba, Seiji Nonoguchi
-
Patent number: 10403680Abstract: A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.Type: GrantFiled: March 16, 2016Date of Patent: September 3, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Kazuhiro Ohba, Hiroaki Sei, Seiji Nonoguchi, Takeyuki Sone, Minoru Ikarashi
-
Publication number: 20190252609Abstract: A switch device according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).Type: ApplicationFiled: September 12, 2017Publication date: August 15, 2019Inventors: HIROAKI SEI, KAZUHIRO OHBA, TAKEYUKI SONE, SEIJI NONOGUCHI, MINORU IKARASHI
-
Patent number: 10299461Abstract: Provided is a water absorbent sheet retaining mat which can retain a water absorbent sheet easily and surely. A water absorbent sheet retaining mat for retaining a water absorbent sheet having a first polygonal contour, includes: a mat member having a second polygonal contour defined by mutually opposing a first main plane and a second main plane; and at least one retaining member having a slit member including at least one slit formed in a top surface at a predetermined height from the first main plane for accepting a part of perimeter of the water absorbent sheet being inserted therein, wherein the water absorbent sheet is laid on the first main plane, and then the above purpose is accomplished.Type: GrantFiled: May 21, 2012Date of Patent: May 28, 2019Assignee: EARTH PET CO., LTD.Inventors: Seiji Nonoguchi, Tsuyoshi Nakata
-
Patent number: 10186658Abstract: Provided is a storage apparatus provided with a plurality of storage elements having storage layers comprising a plurality of layers and electrodes, one layer among the plurality of layers being extended in a first direction and being shared by the plurality of storage elements disposed in the first direction, the electrodes being extended in a second direction that differs from the first direction and being shared by the plurality of storage elements disposed in the second direction.Type: GrantFiled: November 21, 2013Date of Patent: January 22, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Seiji Nonoguchi, Takeyuki Sone, Minoru Ikarashi, Hiroaki Narisawa, Katsuhisa Aratani