Abstract: A semiconductor storage device includes: a memory section including memory cell groups; a redundancy circuit which stops to access the memory section when the redundancy circuit section is activated, and to activate one of the redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is activated; a redundancy decoder which accesses one of the redundancy memory cell groups corresponding to an input selection signal; and a decoder which accesses one of the memory cell groups corresponding to an input address signal, and stops to access the memory cell groups in response to a selection signal. In a normal mode, an access to the redundancy memory section is permitted. In a redundancy circuit inactivation mode, an access to the redundancy memory section is prohibited. Memory tests of a storage device under various conditions can be performed in a short time.

Abstract: A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the memory array in the test mode is performed in accordance with a second signal, and a test of a plurality of items of output data from the memory array is conducted in the test mode and results of the test are output. It is so arranged that a desired test is conducted in the test mode based upon a third signal unrelated to the first signal and second signal.

Abstract: A semiconductor storage device includes: a memory section including memory cell groups; a redundancy circuit which stops to access the memory section when the redundancy circuit section is activated, and to activate one of the redundancy memory cell groups corresponding to an address signal when the redundancy circuit section is activated; a redundancy decoder which accesses one of the redundancy memory cell groups corresponding to an input selection signal; and a decoder which accesses one of the memory cell groups corresponding to an input address signal, and stops to access the memory cell groups in response to a selection signal. In a normal mode, an access to the redundancy memory section is permitted. In a redundancy circuit inactivation mode, an access to the redundancy memory section is prohibited. Memory tests of a storage device under various conditions can be performed in a short time.

Abstract: A semiconductor memory device is adapted so that access time can be measured accurately when the device is in a test mode. A read or write operation of a memory array in the normal mode is performed in accordance with a first signal, a read or write operation of the memory array in the test mode is performed in accordance with a second signal, and a test of a plurality of items of output data from the memory array is conducted in the test mode and results of the test are output. It is so arranged that a desired test is conducted in the test mode based upon a third signal unrelated to the first signal and second signal.

Abstract: According to one embodiment, a semiconductor memory device can generate a decoder enable signal (YREDB) that can enable and disable a decoder circuit according to external address signals such that the decoder circuit is enabled when ordinary memory cells are accessed and disabled when redundant memory cells are accessed. The semiconductor memory device may include redundancy circuits (010) that may be placed in a first state when an ordinary memory cell is accessed and in a second state when a redundant memory cell is accessed. A combining circuit can activate the decoder enable signal (YREDB) when the redundancy circuits (010) are in the first state and deactivate the decoder enable signal (YREDB) when the redundancy circuits (010) are in the second state. In addition, a pulse generator (011) can provide an ordinary mode pulse (YRDB) in synchronism with all external clock.

Abstract: A semiconductor dynamic random access memory device has a memory cell array divided into columns of memory cell blocks equal to a natural number except powers of two such as, for example, six and arranged in rows and columns, redundant memory cells are formed in two columns of memory cell blocks so as to equalize the loads driven by decoder units of a column address decoder, and the memory cell blocks are respectively formed in areas equal in width to one another so as to equalize sub-word lines connected between row address sub-decoders and the regular/redundant memory cells regardless of the number of regular/redundant memory cells incorporated in each memory cell block.

Abstract: A semiconductor storage device (e.g., synchronous DRAM) is configured using a memory cell array on which memory cells are arranged in a matrix form using word lines and bit lines respectively corresponding to rows and columns, which are designated based on address signals being given from the external. Herein, a row address buffer circuit inputs the address signals in synchronization with an external clock signal to provide a row address signal, which is decoded by a row decoder circuit to selectively activate a corresponding word line. Similarly, a column address buffer circuit inputs the address signals to provide a column address signal, which is converted to internal signals designating continuing column addresses of a prescribed burst length. In addition, a column pre-decoder circuit pre-decodes the internal signals in response to a pulse signal so as to produce column address pre-decode signals, which are decoded by a column decoder circuit to produce column selecting signals.

Abstract: In a semiconductor memory device, a semiconductor chip has a plurality of storage regions, a circuit region, and a wiring region having a plurality of first signal lines and a plurality of second signal lines. Each second signal line is laid out between the first signal lines adjacent to each other and has a wiring length smaller than that of each first signal line. The wiring region has a portion where wiring lines are densely laid out and a portion where wiring lines are sparsely laid out. The second signal lines are laid out in the wiring region of the semiconductor chip while being separated from the first signal lines adjacent to the second signal lines by a minimum distance between signal lines or more, which is determined on the basis of a design rule. The plurality of first signal lines are laid out in the wiring region of the semiconductor chip at an interval (K) obtained by K.gtoreq.

Abstract: In a substrate potential control circuit, first and second substrate potential detection circuits have different intersected characteristics of Vcc versus V.sub.SUB detection level and produce, in response to a substrate potential V.sub.SUB, first and second substrate potential detection signals SUBUP1 and SUBUP2, respectively. A composition circuit composes the first and the second substrate potential detection signals SUBUP1 and SUBUP2 to produce a composite substrate potential detection signal SUBUP. Responsive to the composite substrate potential detection signal SUBUP, a back bias generation circuit generates a back bias signal BBG. Responsive to the back bias signal BBG, a pumping circuit makes the substrate potential V.sub.SUB by pumping.