Abstract: Each chip arranged in each crossbar switch creates and issues, if a packet is input, a log collection packet for collecting a log of the packet. Each chip collects a log related to a transfer of the input packet. Each chip embeds, in the issued log collection packet or a log collection packet transferred from a crossbar switch in a previous stage, the collected log. If a transfer destination of the packet is other than the crossbar switches, each chip stores, in a storage space, the log embedded in the log collection packet and then transfers, to the transfer destination, only an original packet in which the log is deleted. In contrast, if the transfer destination is a crossbar switch, each chip transfers the log collection packet to a crossbar switch in a next stage.

Abstract: An information transfer device includes a storing unit. The information transfer device includes an acquiring unit that acquires information requested by a send request or a re-send request from the storage device. The information transfer device includes a sending unit that sends the information acquired by the acquiring unit to the information processing apparatus. The information transfer device includes a retaining unit that stores the information acquired by the acquiring unit after a predetermined time period has elapsed to the storing unit. The sending unit sends the information stored in the storing unit to the information processing apparatus when the acquiring unit has not acquired the information requested by the re-send request from the storage device within the predetermined time period after the re-send request was received.

Abstract: In an information processing apparatus that includes a first and second semiconductor devices that are connected to each other and also includes a system control device that is connected to the first and second semiconductor devices, the timers that are mounted on the semiconductor devices are all synchronized by successively performing a timer correction process between a semiconductor device in which the timer is synchronized and a semiconductor device, adjacent to the semiconductor device, in which the timer is not synchronized, and, when an error occurs in the information processing device, the value in the synchronized timer and the error information are stored in a predetermined register.

Abstract: A register access control circuit and method includes extracting data written to a plurality of registers by specifying the common address in response to read access to a common address, comparing the data extracted from the respective registers, and outputting the data extracted from one of the registers as read data when the data extracted from the respective registers match.

Abstract: In an information processing apparatus that includes a first and second semiconductor devices that are connected to each other and also includes a system control device that is connected to the first and second semiconductor devices, the timers that are mounted on the semiconductor devices are all synchronized by successively performing a timer correction process between a semiconductor device in which the timer is synchronized and a semiconductor device, adjacent to the semiconductor device, in which the timer is not synchronized, and, when an error occurs in the information processing device, the value in the synchronized timer and the error information are stored in a predetermined register.

Abstract: Each chip arranged in each crossbar switch creates and issues, if a packet is input, a log collection packet for collecting a log of the packet. Each chip collects a log related to a transfer of the input packet. Each chip embeds, in the issued log collection packet or a log collection packet transferred from a crossbar switch in a previous stage, the collected log. If a transfer destination of the packet is other than the crossbar switches, each chip stores, in a storage space, the log embedded in the log collection packet and then transfers, to the transfer destination, only an original packet in which the log is deleted. In contrast, if the transfer destination is a crossbar switch, each chip transfers the log collection packet to a crossbar switch in a next stage.