Patents by Inventor Seiji Yaegashi

Seiji Yaegashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7728353
    Abstract: A semiconductor device includes a mask layer having openings on a substrate, a GaN-based semiconductor layer selectively formed on the substrate with the mask layer that serves as a mask, a gate electrode and either a source electrode or an emitter electrode formed on the GaN-based semiconductor layer, and a drain electrode or a collector electrode connected on a surface of the first semiconductor layer that faces the GaN-based semiconductor layer or an opposite side of the first semiconductor layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: June 1, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Seiji Yaegashi, Takeshi Kawasaki, Ken Nakata
  • Patent number: 7723751
    Abstract: A semiconductor device includes a substrate, a SiC drift layer formed above the substrate, a GaN-based semiconductor layer that is formed on the SiC drift layer and includes a channel layer, a source electrode and a gate electrode formed on the GaN-based semiconductor layer, current blocking regions formed in portions of the SiC drift layer and located below the source and gate electrodes, and a drain electrode formed on a surface that opposes the GaN-based semiconductor layer across the SiC layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Takeshi Kawasaki, Ken Nakata, Seiji Yaegashi
  • Patent number: 7592647
    Abstract: A semiconductor device includes a GaN-based semiconductor layer that is formed on a substrate and an opening region, an electron conduction layer formed on an inner surface of the opening region, an electron supply layer that has a larger band gap than the electron conduction layer and is formed on the electron conduction layer disposed on the inner surface of the opening region, and a gate electrode formed on a side surface of the electron supply layer in the opening region. A source electrode is formed on the GaN-based semiconductor layer. A drain electrode is connected to a surface of the GaN-based semiconductor layer opposite to the source electrode.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 22, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Ken Nakata, Takeshi Kawasaki, Seiji Yaegashi
  • Publication number: 20080079009
    Abstract: A semiconductor device includes a substrate composed of 3C-SiC, a GaN-based semiconductor layer provided on the substrate, a first electrode provided on the GaN-based semiconductor layer, a second electrode coupled to the substrate, and a control electrode controlling a current flowing between the first electrode and the second electrode.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 3, 2008
    Applicant: EUDYNA DEVICES INC.
    Inventor: Seiji YAEGASHI
  • Publication number: 20060220042
    Abstract: A semiconductor device includes a mask layer having openings on a substrate, a GaN-based semiconductor layer selectively formed on the substrate with the mask layer that serves as a mask, a gate electrode and either a source electrode or an emitter electrode formed on the GaN-based semiconductor layer, and a drain electrode or a collector electrode connected on a surface of the first semiconductor layer that faces the GaN-based semiconductor layer or an opposite side of the first semiconductor layer.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: EUDYNA DEVICES INC.
    Inventors: Seiji Yaegashi, Takeshi Kawasaki, Ken Nakata
  • Publication number: 20060219997
    Abstract: A semiconductor device includes a substrate, a SiC drift layer formed above the substrate, a GaN-based semiconductor layer that is formed on the SiC drift layer and includes a channel layer, a source electrode and a gate electrode formed on the GaN-based semiconductor layer, current blocking regions formed in portions of the SiC drift layer and located below the source and gate electrodes, and a drain electrode formed on a surface that opposes the GaN-based semiconductor layer across the SiC layer.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: EUDYNA DEVICES INC.
    Inventors: Takeshi Kawasaki, Ken Nakata, Seiji Yaegashi
  • Publication number: 20060220060
    Abstract: A semiconductor device includes a GaN-based semiconductor layer that is formed on a substrate and an opening region, an electron conduction layer formed on an inner surface of the opening region, an electron supply layer that has a larger band gap than the electron conduction layer and is formed on the electron conduction layer disposed on the inner surface of the opening region, and a gate electrode formed on a side surface of the electron supply layer in the opening region. A source electrode is formed on the GaN-based semiconductor layer. A drain electrode is connected to a surface of the GaN-based semiconductor layer opposite to the source electrode.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: EUDYNA DEVICES INC.
    Inventors: Ken Nakata, Takeshi Kawasaki, Seiji Yaegashi
  • Publication number: 20060220065
    Abstract: A semiconductor device includes a substrate, a GaN-based semiconductor layer formed on the substrate, a gate electrode embedded in the GaN-based semiconductor layer, a source electrode and a drain electrode formed on both sides of the gate electrode, a first recess portion formed between the gate electrode and the source electrode, and a second recess portion formed between the gate electrode and the drain electrode. The first recess portion has a depth deeper than that of the second recess portion.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: EUDYNA DEVICES INC.
    Inventors: Takeshi Kawasaki, Ken Nakata, Seiji Yaegashi
  • Patent number: 6784064
    Abstract: A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask layer. The photomask has a pattern thereon for forming the emitter. The pattern is defined by a first area R associated with the shape of the emitter to be formed, and a plurality of second areas T1 to T4. Each of the second areas T1 to T4 includes first and second sides S1 and S2 meeting each other to form an acute angle therebetween, and a third side S3 in contact with the first area R. In each of the second areas T1 to T4, one side S3 of the two sides meeting each other to form a right angle therebetween is in contact with one side of the area R, whereas the other side S1 is connected to another side of the first area R to form a line segment.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: August 31, 2004
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Kenji Kotani, Masaki Yanagisawa, Hiroshi Yano
  • Patent number: 6664610
    Abstract: This invention provides a new configuration and manufacturing method of the hetero-junction bipolar transistor. According to the invention, the HBT comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter contact layer These layers are sequentially grown on the buffer layer. Since a pre-processing of forming two depressions in the sub-collector layer before growing the collector layer, the top surface of the emitter layer becomes planar surface. This results on the reduction of pits induced in the etching of the emitter contact layer, thus enhances the reliability and the high frequency performance of the HBT.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: December 16, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeshi Kawasaki, Kenji Kotani, Masaki Yanagisawa, Seiji Yaegashi, Hiroshi Yano
  • Publication number: 20030075737
    Abstract: This invention provides a new configuration and manufacturing method of the hetero-junction bipolar transistor. According to the invention, the HBT comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter contact layer These layers are sequentially grown on the buffer layer. Since a pre-processing of forming two depressions in the sub-collector layer before growing the collector layer, the top surface of the emitter layer becomes planar surface. This results on the reduction of pits induced in the etching of the emitter contact layer, thus enhances the reliability and the high frequency performance of the HBT.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 24, 2003
    Inventors: Takeshi Kawasaki, Kenji Kotani, Masaki Yanagisawa, Seiji Yaegashi, Hiroshi Yano
  • Patent number: 6531722
    Abstract: The present invention relates to a hetero-bipolar transistor. This transistor comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer on the buffer layer, a collector layer on the sub-collector layer, a base layer on the collector layer, a wide-gap emitter layer on the base layer and a emitter contact layer on the emitter layer. The emitter layer extends the emitter contact layer, so the edge of the emitter layer is apart from the emitter contact layer and entirely covers the region where the collector layer and the sub-collector layer are overlapped to each other. According to this configuration, the transistor shows the enhanced reliability and the improved high frequency performance.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: March 11, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Kenji Kotani, Masaki Yanagisawa, Hiroshi Yano
  • Publication number: 20020105011
    Abstract: A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask layer. The photomask has a pattern thereon for forming the emitter. The pattern is defined by a first area R associated with the shape of the emitter to be formed, and a plurality of second areas T1 to T4. Each of the second areas T1 to T4 includes first and second sides S1 and S2 meeting each other to form an acute angle therebetween, and a third side S3 in contact with the first area R. In each of the second areas T1 to T4, one side S3 of the two sides meeting each other to form a right angle therebetween is in contact with one side of the area R, whereas the other side S1 is connected to another side of the first area R to form a line segment.
    Type: Application
    Filed: December 27, 2001
    Publication date: August 8, 2002
    Inventors: Seiji Yaegashi, Kenji Kotani, Masaki Yanagisawa, Hiroshi Yano
  • Patent number: 5537278
    Abstract: A thin film magnetic head comprises a non-magnetic oxide substrate 11 and a soft magnetic thin film 12 of an Fe-Si-Al alloy or the like laminated on the substrate 11. A reaction prevention film 40 of magnesia or an oxide material containing magnesia is formed in the interface between the substrate and soft magnetic thin film. The film 40 has a function of preventing the reaction between the substrate 11 and the thin film 12 to preclude magnetic property deterioration of the soft magnetic thin film and also reproduced output reduction and further preclude increase of the residual stress in the interface between the substrate and soft magnetic thin film, thus permitting excellent magnetic properties to be obtained.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: July 16, 1996
    Assignee: Japan Energy Corporation
    Inventors: Seiji Yaegashi, Kiyoshi Ogino, Hideo Segawa
  • Patent number: 5306696
    Abstract: A method of producing a superconductor of metal oxides having the following composition:(M.sub.1-x Ca.sub.x)(Ba.sub.1-y Sr.sub.y).sub.2 Cu.sub.4 O.sub.8wherein M stands for a rare earth element, x is 0 or a positive number of less than 1 and y is 0 or a positive number of less than 1, is disclosed, which includes hydrdolyzing an organic solvent solution or dispersion containing (a) alkoxide or fine particulate of a hydroxide of the rare earth element M, (b) alkoxides orfine particulate of hydroxides of Ca, Ba and Sr and (c) alkoxide, nitrate or fine particulate of hydroxide of copper in presence of water and nitrate ions. The alkoxides or hydroxides of Ca and Sr are present only when x and y are not zero, respectively. The hydrolyzed product is then dried, shaped and pyrolyzed to obtain the superconductor.
    Type: Grant
    Filed: December 10, 1990
    Date of Patent: April 26, 1994
    Assignees: Kabushiki-Gaisha Arubakku Kohporehiosentah, Nippon Mining Co., Ltd., Ishikawajima-Harima Jukogyo Kabushiki Kaisha, International Superconductivity Technology Center
    Inventors: Hirohiko Murakami, Junya Nishino, Seiji Yaegashi, Yu Shiohara, Shoji Tanaka
  • Patent number: 5236890
    Abstract: A method of producing a superconductor of metal oxides which includes subjecting an organic solvent solution containing (a) an alkoxide of a rare earth element, (b) an alkoxide of an alkaline earth metal and (c) copper alkoxide or cupric nitrate to hydrolysis in the presence of water and nitrate ions, thereby forming a mixture containing a gel-like substance. The gel-like substance is, after being dried and formed into a desired shape, pyrolyzed at a temperature of 600.degree.-950.degree.C. to form a superconductor of oxides of the rare earth, the alkaline earth metal and copper.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: August 17, 1993
    Assignees: Kabushiki-Gaisha Arubakku Kohporehtosentah, Nippon Mining Co., Ltd., Ishikawajima-Harima Jukogyo Kabushiki Kaisha, The International Superconductivity Technology Center
    Inventors: Hirohiko Murakami, Junya Nishino, Seiji Yaegashi, Yu Shiohara, Shoji Tanaka