Patents by Inventor Seiya SAITO
Seiya SAITO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194252Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line.Type: ApplicationFiled: February 22, 2024Publication date: June 13, 2024Inventors: Seiya SAITO, Yuto YAKUBO, Tatsuya ONUKI, Shuhei NAGATSUKA
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Publication number: 20240186170Abstract: A member for a semiconductor manufacturing apparatus includes: a ceramic plate that has a wafer placement surface at an upper surface thereof; a plug disposition hole that extends through the ceramic plate in an up-down direction and that has a truncated conical space whose upper opening is larger than a lower opening thereof; a truncated conical plug that is disposed in the plug disposition hole, that allows gas to flow in the up-down direction, and whose upper surface is larger than a lower surface thereof; an adhesive layer that is provided between the plug disposition hole and the truncated conical plug; an electrically conductive baseplate that is joined to a lower surface of the ceramic plate through a joint layer; and a gas supply path that is provided in the baseplate and the joint layer and that supplies gas to the truncated conical plug.Type: ApplicationFiled: July 5, 2023Publication date: June 6, 2024Applicant: NGK INSULATORS, LTD.Inventors: Natsuki HIRATA, Shinya YOSHIDA, Tatsuya KUNO, Seiya INOUE, Taro USAMI, Kenji YONEMOTO, Aoi SAITO
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Publication number: 20240174230Abstract: An object of the present invention is to provide a vehicle control device capable of improving ride comfort of a driver. A lane change detection unit 205 of a vehicle control device 200 determines a possibility of cut-in of an adjacent vehicle immediately in front of an own vehicle on the basis of an adjacent vehicle relationship value (for example, a relative speed between the own vehicle and the adjacent vehicle) in an advancing direction. An acceleration/deceleration control unit 206 corrects acceleration/deceleration of the own vehicle on the basis of the possibility of the cut-in determined on the basis of the adjacent vehicle relationship value in the advancing direction.Type: ApplicationFiled: February 28, 2022Publication date: May 30, 2024Applicant: HITACHI ASTEMO, LTD.Inventors: Takayuki SAITO, Masashi SEIMIYA, Taku TAKAHAMA, Keisuke TAKEUCHI, Yuta TSURUMOTO, Seiya ISHII
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Patent number: 11968820Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.Type: GrantFiled: February 11, 2020Date of Patent: April 23, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Onuki, Yuto Yakubo, Seiya Saito
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Patent number: 11948626Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line.Type: GrantFiled: March 16, 2020Date of Patent: April 2, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Seiya Saito, Yuto Yakubo, Tatsuya Onuki, Shuhei Nagatsuka
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Patent number: 11923707Abstract: A battery protection circuit with a novel configuration and a power storage device including the battery protection circuit are provided. The battery protection circuit includes a switch circuit for controlling charge and discharge of a battery cell; the switch circuit includes a mechanical relay, a first transistor, and a second transistor; the switch circuit has a function of controlling electrical connection between a first terminal and a second terminal; the mechanical relay has a function of breaking electrical connection between the first terminal and the second terminal; the first transistor has a function of supplying first current between the first terminal and the second terminal; the second transistor has a function of supplying second current between the first terminal and the second terminal; and the first current is higher than the second current.Type: GrantFiled: November 6, 2019Date of Patent: March 5, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takayuki Ikeda, Munehiro Kozuma, Takanori Matsuzaki, Akio Suzuki, Seiya Saito
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Patent number: 11869627Abstract: A semiconductor device is provided which includes a first control circuit including a first transistor in a silicon substrate channel, a second control circuit provided over the first control circuit, a memory circuit provided over the second control circuit, and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal. In a first period for reading data from the memory circuit to the first control circuit, the second control circuit controls whether the global bit line and the inverted global bit line from which electric charge is discharged are charged or not in accordance with the data read from the memory circuit.Type: GrantFiled: May 12, 2020Date of Patent: January 9, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuto Yakubo, Seiya Saito, Tatsuya Onuki
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Patent number: 11476862Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit.Type: GrantFiled: October 10, 2019Date of Patent: October 18, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Onuki, Yuto Yakubo, Kiyoshi Kato, Seiya Saito
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Publication number: 20220246185Abstract: Provision of a novel semiconductor device. The semiconductor device includes a first control circuit including a first transistor using a silicon substrate for a channel; a second control circuit provided over the first control circuit, which includes a second transistor using a metal oxide for a channel; a memory circuit provided over the second control circuit, which includes a third transistor using a metal oxide for a channel; and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal.Type: ApplicationFiled: May 12, 2020Publication date: August 4, 2022Inventors: Yuto YAKUBO, Seiya SAITO, Tatsuya ONUKI
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Publication number: 20220180920Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line.Type: ApplicationFiled: March 16, 2020Publication date: June 9, 2022Inventors: Seiya SAITO, Yuto YAKUBO, Tatsuya ONUKI, Shuhei NAGATSUKA
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Publication number: 20220093600Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.Type: ApplicationFiled: February 11, 2020Publication date: March 24, 2022Inventors: Tatsuya ONUKI, Yuto YAKUBO, Seiya SAITO
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Publication number: 20220085073Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.Type: ApplicationFiled: November 19, 2019Publication date: March 17, 2022Inventors: Tatsuya ONUKI, Yuto YAKUBO, Yuki OKAMOTO, Seiya SAITO, Kiyoshi KATO, Shunpei YAMAZAKI
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Publication number: 20220052535Abstract: A battery protection circuit with a novel configuration and a power storage device including the battery protection circuit are provided. The battery protection circuit includes a switch circuit for controlling charge and discharge of a battery cell; the switch circuit includes a mechanical relay, a first transistor, and a second transistor; the switch circuit has a function of controlling electrical connection between a first terminal and a second terminal; the mechanical relay has a function of breaking electrical connection between the first terminal and the second terminal; the first transistor has a function of supplying first current between the first terminal and the second terminal; the second transistor has a function of supplying second current between the first terminal and the second terminal; and the first current is higher than the second current.Type: ApplicationFiled: November 6, 2019Publication date: February 17, 2022Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Takayuki IKEDA, Munehiro KOZUMA, Takanori MATSUZAKI, Akio SUZUKI, Seiya SAITO
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Publication number: 20210376848Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit.Type: ApplicationFiled: October 10, 2019Publication date: December 2, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tatsuya ONUKI, Yuto YAKUBO, Kiyoshi KATO, Seiya SAITO