Abstract: A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line.

Abstract: A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line.

Abstract: A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor.

Abstract: A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor.

Abstract: Transistors formed in one identical diffusion layer and performing complementary operations are generally arranged symmetrically with respect to the diffusion layer. A semiconductor integrated device using a layout capable of partially avoiding restriction on the design of the semiconductor integrated circuit device and reducing the size and economizing the manufacturing cost is provided by breaking the stereotype idea. The size of the semiconductor integrated circuit device can be decreased further by arranging two transistors formed in one identical diffusion layer and conducting complementary operations by intentionally arranging them in an asymmetric pattern.

Abstract: Transistors formed in one identical diffusion layer and performing complementary operations are generally arranged symmetrically with respect to the diffusion layer. A semiconductor integrated device using a layout capable of partially avoiding restriction on the design of the semiconductor integrated circuit device and reducing the size and economizing the manufacturing cost is provided by breaking the stereotype idea. The size of the semiconductor integrated circuit device can be decreased further by arranging two transistors formed in one identical diffusion layer and conducting complementary operations by intentionally arranging them in an asymmetric pattern.

Abstract: On a semiconductor integrated circuit chip, multiple equipotential power-line conductors are provided to supply power to circuit elements. First protecting elements are provided for interconnecting the power-line conductors for protecting the circuit elements. A number of input/output pads are also connected to the power-line conductors via second protecting elements. The arrangement is such that the contact positions of any of the first protecting elements and any of the second protecting elements on the power-line conductors are nearer to respective end portions of the conductors than the contact position of any of the circuit elements on the conductors. Each of the contact positions serves as a dividing point for dividing a high potential electrostatic charge into at least two low potential charges.